forked from luck/tmp_suning_uos_patched
net: phy: dp83867: Add TI dp83867 phy
Add support for the TI dp83867 Gigabit ethernet phy device. The DP83867 is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dan Murphy
David S. Miller
parent
f6b59f36b4
commit
2a10154abc
19
Documentation/devicetree/bindings/net/ti,dp83867.txt
Normal file
19
Documentation/devicetree/bindings/net/ti,dp83867.txt
Normal file
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@ -0,0 +1,19 @@
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* Texas Instruments - dp83867 Giga bit ethernet phy
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Required properties:
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- reg - The ID number for the phy, usually a small integer
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- ti,rx_int_delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
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- ti,tx_int_delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values
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- ti,fifo_depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
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for applicable values
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Example:
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ethernet-phy@0 {
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reg = <0>;
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ti,rx_int_delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx_int_delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo_depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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@ -112,6 +112,11 @@ config MICREL_PHY
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---help---
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Supports the KSZ9021, VSC8201, KS8001 PHYs.
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config DP83867_PHY
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tristate "Drivers for Texas Instruments DP83867 Gigabit PHY"
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---help---
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Currently supports the DP83867 PHY.
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config FIXED_PHY
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tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
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depends on PHYLIB
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@ -205,7 +210,6 @@ config MDIO_BCM_UNIMAC
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This hardware can be found in the Broadcom GENET Ethernet MAC
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controllers as well as some Broadcom Ethernet switches such as the
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Starfighter 2 switches.
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endif # PHYLIB
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config MICREL_KS8995MA
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@ -22,6 +22,7 @@ obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
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obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
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obj-$(CONFIG_NATIONAL_PHY) += national.o
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obj-$(CONFIG_DP83640_PHY) += dp83640.o
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obj-$(CONFIG_DP83867_PHY) += dp83867.o
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obj-$(CONFIG_STE10XP) += ste10Xp.o
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obj-$(CONFIG_MICREL_PHY) += micrel.o
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obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
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239
drivers/net/phy/dp83867.c
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239
drivers/net/phy/dp83867.c
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@ -0,0 +1,239 @@
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/*
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* Driver for the Texas Instruments DP83867 PHY
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*
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* Copyright (C) 2015 Texas Instruments Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/ethtool.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#define DP83867_PHY_ID 0x2000a231
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#define DP83867_DEVADDR 0x1f
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#define MII_DP83867_PHYCTRL 0x10
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#define MII_DP83867_MICR 0x12
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#define MII_DP83867_ISR 0x13
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#define DP83867_CTRL 0x1f
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/* Extended Registers */
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#define DP83867_RGMIICTL 0x0032
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#define DP83867_RGMIIDCTL 0x0086
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#define DP83867_SW_RESET BIT(15)
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#define DP83867_SW_RESTART BIT(14)
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/* MICR Interrupt bits */
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#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
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#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
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#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
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#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
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#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
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#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
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#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
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#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
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#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
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#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
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#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
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#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
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/* RGMIICTL bits */
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#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
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#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
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/* PHY CTRL bits */
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#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
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/* RGMIIDCTL bits */
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#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
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struct dp83867_private {
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int rx_id_delay;
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int tx_id_delay;
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int fifo_depth;
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};
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static int dp83867_ack_interrupt(struct phy_device *phydev)
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{
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int err = phy_read(phydev, MII_DP83867_ISR);
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if (err < 0)
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return err;
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return 0;
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}
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static int dp83867_config_intr(struct phy_device *phydev)
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{
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int micr_status;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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micr_status = phy_read(phydev, MII_DP83867_MICR);
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if (micr_status < 0)
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return micr_status;
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micr_status |=
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(MII_DP83867_MICR_AN_ERR_INT_EN |
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MII_DP83867_MICR_SPEED_CHNG_INT_EN |
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MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
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MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
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return phy_write(phydev, MII_DP83867_MICR, micr_status);
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}
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micr_status = 0x0;
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return phy_write(phydev, MII_DP83867_MICR, micr_status);
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}
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#ifdef CONFIG_OF_MDIO
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static int dp83867_of_init(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867 = phydev->priv;
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struct device *dev = &phydev->dev;
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struct device_node *of_node = dev->of_node;
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int ret;
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if (!of_node && dev->parent->of_node)
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of_node = dev->parent->of_node;
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if (!phydev->dev.of_node)
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return -ENODEV;
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ret = of_property_read_u32(of_node, "ti,rx_int_delay",
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&dp83867->rx_id_delay);
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if (ret)
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return ret;
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ret = of_property_read_u32(of_node, "ti,tx_int_delay",
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&dp83867->tx_id_delay);
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if (ret)
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return ret;
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ret = of_property_read_u32(of_node, "ti,fifo_depth",
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&dp83867->fifo_depth);
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if (ret)
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return ret;
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return 0;
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}
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#else
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static int dp83867_of_init(struct phy_device *phydev)
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{
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return 0;
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}
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#endif /* CONFIG_OF_MDIO */
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static int dp83867_config_init(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867;
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int ret;
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u16 val, delay;
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if (!phydev->priv) {
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dp83867 = devm_kzalloc(&phydev->dev, sizeof(*dp83867),
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GFP_KERNEL);
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if (!dp83867)
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return -ENOMEM;
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phydev->priv = dp83867;
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ret = dp83867_of_init(phydev);
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if (ret)
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return ret;
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} else {
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dp83867 = (struct dp83867_private *)phydev->priv;
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}
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if (phy_interface_is_rgmii(phydev)) {
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ret = phy_write(phydev, MII_DP83867_PHYCTRL,
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(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
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if (ret)
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return ret;
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}
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if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
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val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
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DP83867_DEVADDR, phydev->addr);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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val |= DP83867_RGMII_TX_CLK_DELAY_EN;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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val |= DP83867_RGMII_RX_CLK_DELAY_EN;
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phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
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DP83867_DEVADDR, phydev->addr, val);
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delay = (dp83867->rx_id_delay |
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(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
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phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
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DP83867_DEVADDR, phydev->addr, delay);
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}
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return 0;
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}
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static int dp83867_phy_reset(struct phy_device *phydev)
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{
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int err;
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err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
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if (err < 0)
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return err;
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return dp83867_config_init(phydev);
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}
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static struct phy_driver dp83867_driver[] = {
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{
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.phy_id = DP83867_PHY_ID,
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.phy_id_mask = 0xfffffff0,
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.name = "TI DP83867",
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_init = dp83867_config_init,
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.soft_reset = dp83867_phy_reset,
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/* IRQ related */
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.ack_interrupt = dp83867_ack_interrupt,
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.config_intr = dp83867_config_intr,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.driver = {.owner = THIS_MODULE,}
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},
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};
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module_phy_driver(dp83867_driver);
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static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
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{ DP83867_PHY_ID, 0xfffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
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MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
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MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
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MODULE_LICENSE("GPL");
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45
include/dt-bindings/net/ti-dp83867.h
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45
include/dt-bindings/net/ti-dp83867.h
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@ -0,0 +1,45 @@
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/*
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* Device Tree constants for the Texas Instruments DP83867 PHY
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*
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* Author: Dan Murphy <dmurphy@ti.com>
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*
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* Copyright: (C) 2015 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_TI_DP83867_H
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#define _DT_BINDINGS_TI_DP83867_H
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/* PHY CTRL bits */
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#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
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#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
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#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
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#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
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/* RGMIIDCTL internal delay for rx and tx */
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#define DP83867_RGMIIDCTL_250_PS 0x0
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#define DP83867_RGMIIDCTL_500_PS 0x1
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#define DP83867_RGMIIDCTL_750_PS 0x2
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#define DP83867_RGMIIDCTL_1_NS 0x3
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#define DP83867_RGMIIDCTL_1_25_NS 0x4
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#define DP83867_RGMIIDCTL_1_50_NS 0x5
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#define DP83867_RGMIIDCTL_1_75_NS 0x6
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#define DP83867_RGMIIDCTL_2_00_NS 0x7
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#define DP83867_RGMIIDCTL_2_25_NS 0x8
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#define DP83867_RGMIIDCTL_2_50_NS 0x9
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#define DP83867_RGMIIDCTL_2_75_NS 0xa
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#define DP83867_RGMIIDCTL_3_00_NS 0xb
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#define DP83867_RGMIIDCTL_3_25_NS 0xc
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#define DP83867_RGMIIDCTL_3_50_NS 0xd
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#define DP83867_RGMIIDCTL_3_75_NS 0xe
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#define DP83867_RGMIIDCTL_4_00_NS 0xf
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#endif
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