forked from luck/tmp_suning_uos_patched
net/irda: sh_sir: Add SuperH IrDA driver
This is very simple IrDA SIR driver for SuperH. This driver was tested by irdaping/ircp on SH7724 EcoVec24 board Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Kuninori Morimoto
David S. Miller
parent
c85bb41e93
commit
2a6ace1b3d
@ -64,6 +64,16 @@ endchoice
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comment "Dongle support"
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config SH_SIR
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tristate "SuperH SIR on UART"
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depends on IRDA && SUPERH && \
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(CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7723 || \
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CPU_SUBTYPE_SH7724)
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default n
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help
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Say Y here if your want to enable SIR function on SuperH UART
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devices.
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config DONGLE
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bool "Serial dongle support"
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depends on IRTTY_SIR
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@ -22,6 +22,7 @@ obj-$(CONFIG_AU1000_FIR) += au1k_ir.o
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# SIR drivers
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obj-$(CONFIG_IRTTY_SIR) += irtty-sir.o sir-dev.o
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obj-$(CONFIG_BFIN_SIR) += bfin_sir.o
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obj-$(CONFIG_SH_SIR) += sh_sir.o
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# dongle drivers for SIR drivers
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obj-$(CONFIG_ESI_DONGLE) += esi-sir.o
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obj-$(CONFIG_TEKRAM_DONGLE) += tekram-sir.o
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823
drivers/net/irda/sh_sir.c
Normal file
823
drivers/net/irda/sh_sir.c
Normal file
@ -0,0 +1,823 @@
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/*
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* SuperH IrDA Driver
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*
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* Copyright (C) 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on bfin_sir.c
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* Copyright 2006-2009 Analog Devices Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <net/irda/wrapper.h>
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#include <net/irda/irda_device.h>
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#include <asm/clock.h>
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#define DRIVER_NAME "sh_sir"
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#define RX_PHASE (1 << 0)
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#define TX_PHASE (1 << 1)
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#define TX_COMP_PHASE (1 << 2) /* tx complete */
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#define NONE_PHASE (1 << 31)
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#define IRIF_RINTCLR 0x0016 /* DMA rx interrupt source clear */
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#define IRIF_TINTCLR 0x0018 /* DMA tx interrupt source clear */
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#define IRIF_SIR0 0x0020 /* IrDA-SIR10 control */
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#define IRIF_SIR1 0x0022 /* IrDA-SIR10 baudrate error correction */
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#define IRIF_SIR2 0x0024 /* IrDA-SIR10 baudrate count */
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#define IRIF_SIR3 0x0026 /* IrDA-SIR10 status */
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#define IRIF_SIR_FRM 0x0028 /* Hardware frame processing set */
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#define IRIF_SIR_EOF 0x002A /* EOF value */
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#define IRIF_SIR_FLG 0x002C /* Flag clear */
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#define IRIF_UART_STS2 0x002E /* UART status 2 */
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#define IRIF_UART0 0x0030 /* UART control */
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#define IRIF_UART1 0x0032 /* UART status */
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#define IRIF_UART2 0x0034 /* UART mode */
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#define IRIF_UART3 0x0036 /* UART transmit data */
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#define IRIF_UART4 0x0038 /* UART receive data */
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#define IRIF_UART5 0x003A /* UART interrupt mask */
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#define IRIF_UART6 0x003C /* UART baud rate error correction */
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#define IRIF_UART7 0x003E /* UART baud rate count set */
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#define IRIF_CRC0 0x0040 /* CRC engine control */
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#define IRIF_CRC1 0x0042 /* CRC engine input data */
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#define IRIF_CRC2 0x0044 /* CRC engine calculation */
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#define IRIF_CRC3 0x0046 /* CRC engine output data 1 */
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#define IRIF_CRC4 0x0048 /* CRC engine output data 2 */
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/* IRIF_SIR0 */
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#define IRTPW (1 << 1) /* transmit pulse width select */
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#define IRERRC (1 << 0) /* Clear receive pulse width error */
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/* IRIF_SIR3 */
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#define IRERR (1 << 0) /* received pulse width Error */
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/* IRIF_SIR_FRM */
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#define EOFD (1 << 9) /* EOF detection flag */
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#define FRER (1 << 8) /* Frame Error bit */
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#define FRP (1 << 0) /* Frame processing set */
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/* IRIF_UART_STS2 */
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#define IRSME (1 << 6) /* Receive Sum Error flag */
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#define IROVE (1 << 5) /* Receive Overrun Error flag */
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#define IRFRE (1 << 4) /* Receive Framing Error flag */
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#define IRPRE (1 << 3) /* Receive Parity Error flag */
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/* IRIF_UART0_*/
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#define TBEC (1 << 2) /* Transmit Data Clear */
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#define RIE (1 << 1) /* Receive Enable */
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#define TIE (1 << 0) /* Transmit Enable */
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/* IRIF_UART1 */
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#define URSME (1 << 6) /* Receive Sum Error Flag */
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#define UROVE (1 << 5) /* Receive Overrun Error Flag */
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#define URFRE (1 << 4) /* Receive Framing Error Flag */
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#define URPRE (1 << 3) /* Receive Parity Error Flag */
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#define RBF (1 << 2) /* Receive Buffer Full Flag */
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#define TSBE (1 << 1) /* Transmit Shift Buffer Empty Flag */
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#define TBE (1 << 0) /* Transmit Buffer Empty flag */
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#define TBCOMP (TSBE | TBE)
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/* IRIF_UART5 */
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#define RSEIM (1 << 6) /* Receive Sum Error Flag IRQ Mask */
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#define RBFIM (1 << 2) /* Receive Buffer Full Flag IRQ Mask */
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#define TSBEIM (1 << 1) /* Transmit Shift Buffer Empty Flag IRQ Mask */
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#define TBEIM (1 << 0) /* Transmit Buffer Empty Flag IRQ Mask */
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#define RX_MASK (RSEIM | RBFIM)
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/* IRIF_CRC0 */
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#define CRC_RST (1 << 15) /* CRC Engine Reset */
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#define CRC_CT_MASK 0x0FFF
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/************************************************************************
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structure
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************************************************************************/
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struct sh_sir_self {
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void __iomem *membase;
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unsigned int irq;
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struct clk *clk;
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struct net_device *ndev;
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struct irlap_cb *irlap;
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struct qos_info qos;
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iobuff_t tx_buff;
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iobuff_t rx_buff;
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};
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/************************************************************************
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common function
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************************************************************************/
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static void sh_sir_write(struct sh_sir_self *self, u32 offset, u16 data)
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{
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iowrite16(data, self->membase + offset);
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}
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static u16 sh_sir_read(struct sh_sir_self *self, u32 offset)
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{
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return ioread16(self->membase + offset);
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}
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static void sh_sir_update_bits(struct sh_sir_self *self, u32 offset,
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u16 mask, u16 data)
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{
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u16 old, new;
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old = sh_sir_read(self, offset);
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new = (old & ~mask) | data;
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if (old != new)
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sh_sir_write(self, offset, new);
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}
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/************************************************************************
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CRC function
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************************************************************************/
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static void sh_sir_crc_reset(struct sh_sir_self *self)
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{
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sh_sir_write(self, IRIF_CRC0, CRC_RST);
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}
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static void sh_sir_crc_add(struct sh_sir_self *self, u8 data)
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{
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sh_sir_write(self, IRIF_CRC1, (u16)data);
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}
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static u16 sh_sir_crc_cnt(struct sh_sir_self *self)
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{
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return CRC_CT_MASK & sh_sir_read(self, IRIF_CRC0);
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}
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static u16 sh_sir_crc_out(struct sh_sir_self *self)
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{
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return sh_sir_read(self, IRIF_CRC4);
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}
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static int sh_sir_crc_init(struct sh_sir_self *self)
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{
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struct device *dev = &self->ndev->dev;
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int ret = -EIO;
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u16 val;
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sh_sir_crc_reset(self);
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sh_sir_crc_add(self, 0xCC);
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sh_sir_crc_add(self, 0xF5);
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sh_sir_crc_add(self, 0xF1);
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sh_sir_crc_add(self, 0xA7);
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val = sh_sir_crc_cnt(self);
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if (4 != val) {
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dev_err(dev, "CRC count error %x\n", val);
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goto crc_init_out;
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}
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val = sh_sir_crc_out(self);
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if (0x51DF != val) {
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dev_err(dev, "CRC result error%x\n", val);
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goto crc_init_out;
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}
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ret = 0;
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crc_init_out:
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sh_sir_crc_reset(self);
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return ret;
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}
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/************************************************************************
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baud rate functions
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************************************************************************/
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#define SCLK_BASE 1843200 /* 1.8432MHz */
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static u32 sh_sir_find_sclk(struct clk *irda_clk)
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{
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struct cpufreq_frequency_table *freq_table = irda_clk->freq_table;
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struct clk *pclk = clk_get(NULL, "peripheral_clk");
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u32 limit, min = 0xffffffff, tmp;
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int i, index = 0;
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limit = clk_get_rate(pclk);
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clk_put(pclk);
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/* IrDA can not set over peripheral_clk */
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for (i = 0;
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freq_table[i].frequency != CPUFREQ_TABLE_END;
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i++) {
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u32 freq = freq_table[i].frequency;
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if (freq == CPUFREQ_ENTRY_INVALID)
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continue;
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/* IrDA should not over peripheral_clk */
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if (freq > limit)
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continue;
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tmp = freq % SCLK_BASE;
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if (tmp < min) {
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min = tmp;
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index = i;
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}
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}
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return freq_table[index].frequency;
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}
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#define ERR_ROUNDING(a) ((a + 5000) / 10000)
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static int sh_sir_set_baudrate(struct sh_sir_self *self, u32 baudrate)
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{
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struct clk *clk;
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struct device *dev = &self->ndev->dev;
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u32 rate;
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u16 uabca, uabc;
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u16 irbca, irbc;
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u32 min, rerr, tmp;
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int i;
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/* Baud Rate Error Correction x 10000 */
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u32 rate_err_array[] = {
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0000, 0625, 1250, 1875,
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2500, 3125, 3750, 4375,
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5000, 5625, 6250, 6875,
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7500, 8125, 8750, 9375,
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};
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/*
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* FIXME
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*
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* it support 9600 only now
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*/
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switch (baudrate) {
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case 9600:
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break;
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default:
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dev_err(dev, "un-supported baudrate %d\n", baudrate);
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return -EIO;
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}
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clk = clk_get(NULL, "irda_clk");
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if (!clk) {
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dev_err(dev, "can not get irda_clk\n");
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return -EIO;
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}
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clk_set_rate(clk, sh_sir_find_sclk(clk));
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rate = clk_get_rate(clk);
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clk_put(clk);
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dev_dbg(dev, "selected sclk = %d\n", rate);
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/*
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* CALCULATION
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*
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* 1843200 = system rate / (irbca + (irbc + 1))
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*/
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irbc = rate / SCLK_BASE;
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tmp = rate - (SCLK_BASE * irbc);
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tmp *= 10000;
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rerr = tmp / SCLK_BASE;
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min = 0xffffffff;
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irbca = 0;
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for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) {
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tmp = abs(rate_err_array[i] - rerr);
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if (min > tmp) {
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min = tmp;
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irbca = i;
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}
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}
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tmp = rate / (irbc + ERR_ROUNDING(rate_err_array[irbca]));
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if ((SCLK_BASE / 100) < abs(tmp - SCLK_BASE))
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dev_warn(dev, "IrDA freq error margin over %d\n", tmp);
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dev_dbg(dev, "target = %d, result = %d, infrared = %d.%d\n",
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SCLK_BASE, tmp, irbc, rate_err_array[irbca]);
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irbca = (irbca & 0xF) << 4;
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irbc = (irbc - 1) & 0xF;
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if (!irbc) {
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dev_err(dev, "sh_sir can not set 0 in IRIF_SIR2\n");
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return -EIO;
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}
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sh_sir_write(self, IRIF_SIR0, IRTPW | IRERRC);
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sh_sir_write(self, IRIF_SIR1, irbca);
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sh_sir_write(self, IRIF_SIR2, irbc);
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/*
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* CALCULATION
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*
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* BaudRate[bps] = system rate / (uabca + (uabc + 1) x 16)
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*/
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uabc = rate / baudrate;
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uabc = (uabc / 16) - 1;
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uabc = (uabc + 1) * 16;
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tmp = rate - (uabc * baudrate);
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tmp *= 10000;
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rerr = tmp / baudrate;
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min = 0xffffffff;
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uabca = 0;
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for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) {
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tmp = abs(rate_err_array[i] - rerr);
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if (min > tmp) {
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min = tmp;
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uabca = i;
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}
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}
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tmp = rate / (uabc + ERR_ROUNDING(rate_err_array[uabca]));
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if ((baudrate / 100) < abs(tmp - baudrate))
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dev_warn(dev, "UART freq error margin over %d\n", tmp);
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dev_dbg(dev, "target = %d, result = %d, uart = %d.%d\n",
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baudrate, tmp,
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uabc, rate_err_array[uabca]);
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uabca = (uabca & 0xF) << 4;
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uabc = (uabc / 16) - 1;
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sh_sir_write(self, IRIF_UART6, uabca);
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sh_sir_write(self, IRIF_UART7, uabc);
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return 0;
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}
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/************************************************************************
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iobuf function
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************************************************************************/
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static int __sh_sir_init_iobuf(iobuff_t *io, int size)
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{
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io->head = kmalloc(size, GFP_KERNEL);
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if (!io->head)
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return -ENOMEM;
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io->truesize = size;
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io->in_frame = FALSE;
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io->state = OUTSIDE_FRAME;
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io->data = io->head;
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return 0;
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}
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static void sh_sir_remove_iobuf(struct sh_sir_self *self)
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{
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kfree(self->rx_buff.head);
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kfree(self->tx_buff.head);
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self->rx_buff.head = NULL;
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self->tx_buff.head = NULL;
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}
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static int sh_sir_init_iobuf(struct sh_sir_self *self, int rxsize, int txsize)
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{
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int err = -ENOMEM;
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if (self->rx_buff.head ||
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self->tx_buff.head) {
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dev_err(&self->ndev->dev, "iobuff has already existed.");
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return err;
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}
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err = __sh_sir_init_iobuf(&self->rx_buff, rxsize);
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if (err)
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goto iobuf_err;
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err = __sh_sir_init_iobuf(&self->tx_buff, txsize);
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iobuf_err:
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if (err)
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sh_sir_remove_iobuf(self);
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return err;
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}
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/************************************************************************
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status function
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************************************************************************/
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static void sh_sir_clear_all_err(struct sh_sir_self *self)
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{
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/* Clear error flag for receive pulse width */
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sh_sir_update_bits(self, IRIF_SIR0, IRERRC, IRERRC);
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/* Clear frame / EOF error flag */
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sh_sir_write(self, IRIF_SIR_FLG, 0xffff);
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/* Clear all status error */
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sh_sir_write(self, IRIF_UART_STS2, 0);
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}
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static void sh_sir_set_phase(struct sh_sir_self *self, int phase)
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{
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u16 uart5 = 0;
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u16 uart0 = 0;
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switch (phase) {
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case TX_PHASE:
|
||||
uart5 = TBEIM;
|
||||
uart0 = TBEC | TIE;
|
||||
break;
|
||||
case TX_COMP_PHASE:
|
||||
uart5 = TSBEIM;
|
||||
uart0 = TIE;
|
||||
break;
|
||||
case RX_PHASE:
|
||||
uart5 = RX_MASK;
|
||||
uart0 = RIE;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
sh_sir_write(self, IRIF_UART5, uart5);
|
||||
sh_sir_write(self, IRIF_UART0, uart0);
|
||||
}
|
||||
|
||||
static int sh_sir_is_which_phase(struct sh_sir_self *self)
|
||||
{
|
||||
u16 val = sh_sir_read(self, IRIF_UART5);
|
||||
|
||||
if (val & TBEIM)
|
||||
return TX_PHASE;
|
||||
|
||||
if (val & TSBEIM)
|
||||
return TX_COMP_PHASE;
|
||||
|
||||
if (val & RX_MASK)
|
||||
return RX_PHASE;
|
||||
|
||||
return NONE_PHASE;
|
||||
}
|
||||
|
||||
static void sh_sir_tx(struct sh_sir_self *self, int phase)
|
||||
{
|
||||
switch (phase) {
|
||||
case TX_PHASE:
|
||||
if (0 >= self->tx_buff.len) {
|
||||
sh_sir_set_phase(self, TX_COMP_PHASE);
|
||||
} else {
|
||||
sh_sir_write(self, IRIF_UART3, self->tx_buff.data[0]);
|
||||
self->tx_buff.len--;
|
||||
self->tx_buff.data++;
|
||||
}
|
||||
break;
|
||||
case TX_COMP_PHASE:
|
||||
sh_sir_set_phase(self, RX_PHASE);
|
||||
netif_wake_queue(self->ndev);
|
||||
break;
|
||||
default:
|
||||
dev_err(&self->ndev->dev, "should not happen\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int sh_sir_read_data(struct sh_sir_self *self)
|
||||
{
|
||||
u16 val;
|
||||
int timeout = 1024;
|
||||
|
||||
while (timeout--) {
|
||||
val = sh_sir_read(self, IRIF_UART1);
|
||||
|
||||
/* data get */
|
||||
if (val & RBF) {
|
||||
if (val & (URSME | UROVE | URFRE | URPRE))
|
||||
break;
|
||||
|
||||
return (int)sh_sir_read(self, IRIF_UART4);
|
||||
}
|
||||
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
dev_err(&self->ndev->dev, "UART1 %04x : STATUS %04x\n",
|
||||
val, sh_sir_read(self, IRIF_UART_STS2));
|
||||
|
||||
/* read data register for clear error */
|
||||
sh_sir_read(self, IRIF_UART4);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void sh_sir_rx(struct sh_sir_self *self)
|
||||
{
|
||||
int timeout = 1024;
|
||||
int data;
|
||||
|
||||
while (timeout--) {
|
||||
data = sh_sir_read_data(self);
|
||||
if (data < 0)
|
||||
break;
|
||||
|
||||
async_unwrap_char(self->ndev, &self->ndev->stats,
|
||||
&self->rx_buff, (u8)data);
|
||||
self->ndev->last_rx = jiffies;
|
||||
|
||||
if (EOFD & sh_sir_read(self, IRIF_SIR_FRM))
|
||||
continue;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t sh_sir_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct sh_sir_self *self = dev_id;
|
||||
struct device *dev = &self->ndev->dev;
|
||||
int phase = sh_sir_is_which_phase(self);
|
||||
|
||||
switch (phase) {
|
||||
case TX_COMP_PHASE:
|
||||
case TX_PHASE:
|
||||
sh_sir_tx(self, phase);
|
||||
break;
|
||||
case RX_PHASE:
|
||||
if (sh_sir_read(self, IRIF_SIR3))
|
||||
dev_err(dev, "rcv pulse width error occurred\n");
|
||||
|
||||
sh_sir_rx(self);
|
||||
sh_sir_clear_all_err(self);
|
||||
break;
|
||||
default:
|
||||
dev_err(dev, "unknown interrupt\n");
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/************************************************************************
|
||||
|
||||
|
||||
net_device_ops function
|
||||
|
||||
|
||||
************************************************************************/
|
||||
static int sh_sir_hard_xmit(struct sk_buff *skb, struct net_device *ndev)
|
||||
{
|
||||
struct sh_sir_self *self = netdev_priv(ndev);
|
||||
int speed = irda_get_next_speed(skb);
|
||||
|
||||
if ((0 < speed) &&
|
||||
(9600 != speed)) {
|
||||
dev_err(&ndev->dev, "support 9600 only (%d)\n", speed);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
netif_stop_queue(ndev);
|
||||
|
||||
self->tx_buff.data = self->tx_buff.head;
|
||||
self->tx_buff.len = 0;
|
||||
if (skb->len)
|
||||
self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
|
||||
self->tx_buff.truesize);
|
||||
|
||||
sh_sir_set_phase(self, TX_PHASE);
|
||||
dev_kfree_skb(skb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_sir_ioctl(struct net_device *ndev, struct ifreq *ifreq, int cmd)
|
||||
{
|
||||
/*
|
||||
* FIXME
|
||||
*
|
||||
* This function is needed for irda framework.
|
||||
* But nothing to do now
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct net_device_stats *sh_sir_stats(struct net_device *ndev)
|
||||
{
|
||||
struct sh_sir_self *self = netdev_priv(ndev);
|
||||
|
||||
return &self->ndev->stats;
|
||||
}
|
||||
|
||||
static int sh_sir_open(struct net_device *ndev)
|
||||
{
|
||||
struct sh_sir_self *self = netdev_priv(ndev);
|
||||
int err;
|
||||
|
||||
clk_enable(self->clk);
|
||||
err = sh_sir_crc_init(self);
|
||||
if (err)
|
||||
goto open_err;
|
||||
|
||||
sh_sir_set_baudrate(self, 9600);
|
||||
|
||||
self->irlap = irlap_open(ndev, &self->qos, DRIVER_NAME);
|
||||
if (!self->irlap)
|
||||
goto open_err;
|
||||
|
||||
/*
|
||||
* Now enable the interrupt then start the queue
|
||||
*/
|
||||
sh_sir_update_bits(self, IRIF_SIR_FRM, FRP, FRP);
|
||||
sh_sir_read(self, IRIF_UART1); /* flag clear */
|
||||
sh_sir_read(self, IRIF_UART4); /* flag clear */
|
||||
sh_sir_set_phase(self, RX_PHASE);
|
||||
|
||||
netif_start_queue(ndev);
|
||||
|
||||
dev_info(&self->ndev->dev, "opened\n");
|
||||
|
||||
return 0;
|
||||
|
||||
open_err:
|
||||
clk_disable(self->clk);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int sh_sir_stop(struct net_device *ndev)
|
||||
{
|
||||
struct sh_sir_self *self = netdev_priv(ndev);
|
||||
|
||||
/* Stop IrLAP */
|
||||
if (self->irlap) {
|
||||
irlap_close(self->irlap);
|
||||
self->irlap = NULL;
|
||||
}
|
||||
|
||||
netif_stop_queue(ndev);
|
||||
|
||||
dev_info(&ndev->dev, "stoped\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct net_device_ops sh_sir_ndo = {
|
||||
.ndo_open = sh_sir_open,
|
||||
.ndo_stop = sh_sir_stop,
|
||||
.ndo_start_xmit = sh_sir_hard_xmit,
|
||||
.ndo_do_ioctl = sh_sir_ioctl,
|
||||
.ndo_get_stats = sh_sir_stats,
|
||||
};
|
||||
|
||||
/************************************************************************
|
||||
|
||||
|
||||
platform_driver function
|
||||
|
||||
|
||||
************************************************************************/
|
||||
static int __devinit sh_sir_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *ndev;
|
||||
struct sh_sir_self *self;
|
||||
struct resource *res;
|
||||
char clk_name[8];
|
||||
void __iomem *base;
|
||||
unsigned int irq;
|
||||
int err = -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (!res || irq < 0) {
|
||||
dev_err(&pdev->dev, "Not enough platform resources.\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
ndev = alloc_irdadev(sizeof(*self));
|
||||
if (!ndev)
|
||||
goto exit;
|
||||
|
||||
base = ioremap_nocache(res->start, resource_size(res));
|
||||
if (!base) {
|
||||
err = -ENXIO;
|
||||
dev_err(&pdev->dev, "Unable to ioremap.\n");
|
||||
goto err_mem_1;
|
||||
}
|
||||
|
||||
self = netdev_priv(ndev);
|
||||
err = sh_sir_init_iobuf(self, IRDA_SKB_MAX_MTU, IRDA_SIR_MAX_FRAME);
|
||||
if (err)
|
||||
goto err_mem_2;
|
||||
|
||||
snprintf(clk_name, sizeof(clk_name), "irda%d", pdev->id);
|
||||
self->clk = clk_get(&pdev->dev, clk_name);
|
||||
if (IS_ERR(self->clk)) {
|
||||
dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
|
||||
goto err_mem_3;
|
||||
}
|
||||
|
||||
irda_init_max_qos_capabilies(&self->qos);
|
||||
|
||||
ndev->netdev_ops = &sh_sir_ndo;
|
||||
ndev->irq = irq;
|
||||
|
||||
self->membase = base;
|
||||
self->ndev = ndev;
|
||||
self->qos.baud_rate.bits &= IR_9600; /* FIXME */
|
||||
self->qos.min_turn_time.bits = 1; /* 10 ms or more */
|
||||
|
||||
irda_qos_bits_to_value(&self->qos);
|
||||
|
||||
err = register_netdev(ndev);
|
||||
if (err)
|
||||
goto err_mem_4;
|
||||
|
||||
platform_set_drvdata(pdev, ndev);
|
||||
|
||||
if (request_irq(irq, sh_sir_irq, IRQF_DISABLED, "sh_sir", self)) {
|
||||
dev_warn(&pdev->dev, "Unable to attach sh_sir interrupt\n");
|
||||
goto err_mem_4;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "SuperH IrDA probed\n");
|
||||
|
||||
goto exit;
|
||||
|
||||
err_mem_4:
|
||||
clk_put(self->clk);
|
||||
err_mem_3:
|
||||
sh_sir_remove_iobuf(self);
|
||||
err_mem_2:
|
||||
iounmap(self->membase);
|
||||
err_mem_1:
|
||||
free_netdev(ndev);
|
||||
exit:
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __devexit sh_sir_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *ndev = platform_get_drvdata(pdev);
|
||||
struct sh_sir_self *self = netdev_priv(ndev);
|
||||
|
||||
if (!self)
|
||||
return 0;
|
||||
|
||||
unregister_netdev(ndev);
|
||||
clk_put(self->clk);
|
||||
sh_sir_remove_iobuf(self);
|
||||
iounmap(self->membase);
|
||||
free_netdev(ndev);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sh_sir_driver = {
|
||||
.probe = sh_sir_probe,
|
||||
.remove = __devexit_p(sh_sir_remove),
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init sh_sir_init(void)
|
||||
{
|
||||
return platform_driver_register(&sh_sir_driver);
|
||||
}
|
||||
|
||||
static void __exit sh_sir_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sh_sir_driver);
|
||||
}
|
||||
|
||||
module_init(sh_sir_init);
|
||||
module_exit(sh_sir_exit);
|
||||
|
||||
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
|
||||
MODULE_DESCRIPTION("SuperH IrDA driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user