forked from luck/tmp_suning_uos_patched
ARM: Merge for-2635/s3c6410-clock
Merge branch 'for-2635/s3c6410-clock' into for-linus/samsung2
This commit is contained in:
commit
2abbfb26de
@ -88,6 +88,12 @@ struct clk clk_48m = {
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.enable = clk_48m_ctrl,
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};
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struct clk clk_xusbxti = {
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.name = "xusbxti",
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.id = -1,
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.rate = 48000000,
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};
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static int inline s3c64xx_gate(void __iomem *reg,
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struct clk *clk,
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int enable)
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@ -518,6 +524,11 @@ static struct clk clk_iis_cd1 = {
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.id = -1,
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};
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static struct clk clk_iisv4_cd = {
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.name = "iis_cdclk_v4",
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.id = -1,
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};
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static struct clk clk_pcm_cd = {
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.name = "pcm_cdclk",
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.id = -1,
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@ -549,6 +560,19 @@ static struct clksrc_sources clkset_audio1 = {
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.nr_sources = ARRAY_SIZE(clkset_audio1_list),
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};
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static struct clk *clkset_audio2_list[] = {
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[0] = &clk_mout_epll.clk,
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[1] = &clk_dout_mpll,
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[2] = &clk_fin_epll,
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[3] = &clk_iisv4_cd,
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[4] = &clk_pcm_cd,
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};
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static struct clksrc_sources clkset_audio2 = {
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.sources = clkset_audio2_list,
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.nr_sources = ARRAY_SIZE(clkset_audio2_list),
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};
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static struct clk *clkset_camif_list[] = {
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&clk_h2,
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};
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@ -650,6 +674,16 @@ static struct clksrc_clk clksrcs[] = {
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.reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
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.reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
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.sources = &clkset_audio1,
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}, {
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.clk = {
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.name = "audio-bus",
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.id = -1, /* There's only one IISv4 port */
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.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
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.enable = s3c64xx_sclk_ctrl,
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},
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.reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
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.reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
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.sources = &clkset_audio2,
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}, {
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.clk = {
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.name = "irda-bus",
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@ -749,6 +783,7 @@ static struct clk *clks1[] __initdata = {
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&clk_ext_xtal_mux,
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&clk_iis_cd0,
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&clk_iis_cd1,
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&clk_iisv4_cd,
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&clk_pcm_cd,
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&clk_mout_epll.clk,
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&clk_mout_mpll.clk,
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@ -762,6 +797,7 @@ static struct clk *clks[] __initdata = {
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&clk_27m,
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&clk_48m,
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&clk_h2,
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&clk_xusbxti,
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};
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/**
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@ -33,6 +33,7 @@
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#define S3C_PCLK_GATE S3C_CLKREG(0x34)
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#define S3C_SCLK_GATE S3C_CLKREG(0x38)
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#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
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#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
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/* CLKDIV0 */
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#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
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@ -74,6 +74,7 @@ extern struct clk clk_ext;
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extern struct clk clk_h2;
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extern struct clk clk_27m;
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extern struct clk clk_48m;
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extern struct clk clk_xusbxti;
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extern int clk_default_setrate(struct clk *clk, unsigned long rate);
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extern struct clk_ops clk_ops_def_setrate;
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