forked from luck/tmp_suning_uos_patched
sh: Initial support for the MX-G CPU.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
b9e393c2ba
commit
2ad699080b
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@ -167,6 +167,12 @@ config CPU_SUBTYPE_SH7263
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select CPU_SH2A
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select CPU_HAS_FPU
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config CPU_SUBTYPE_MXG
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bool "Support MX-G processor"
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select CPU_SH2A
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help
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Select MX-G if running on an R8A03022BG part.
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# SH-3 Processor Support
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config CPU_SUBTYPE_SH7705
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@ -560,7 +566,7 @@ config SH_TMU
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config SH_CMT
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def_bool y
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prompt "CMT timer support"
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depends on CPU_SH2
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depends on CPU_SH2 && !CPU_SUBTYPE_MXG
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help
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This enables the use of the CMT as the system timer.
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@ -578,6 +584,7 @@ config SH_TIMER_IRQ
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default "86" if CPU_SUBTYPE_SH7619
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default "140" if CPU_SUBTYPE_SH7206
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default "142" if CPU_SUBTYPE_SH7203
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default "238" if CPU_SUBTYPE_MXG
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default "16"
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config SH_PCLK_FREQ
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@ -588,7 +595,7 @@ config SH_PCLK_FREQ
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default "33333333" if CPU_SUBTYPE_SH7770 || \
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CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
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CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
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CPU_SUBTYPE_SH7263
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CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG
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default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
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default "66000000" if CPU_SUBTYPE_SH4_202
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default "50000000"
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@ -29,16 +29,17 @@ config EARLY_SCIF_CONSOLE
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config EARLY_SCIF_CONSOLE_PORT
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hex
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depends on EARLY_SCIF_CONSOLE
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default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
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default "0xffe00000" if CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
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default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
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default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
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default "0xf8420000" if CPU_SUBTYPE_SH7619
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default "0xff804000" if CPU_SUBTYPE_MXG
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default "0xffc30000" if CPU_SUBTYPE_SHX3
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default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
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CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
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default "0xffe80000" if CPU_SH4
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default "0xffea0000" if CPU_SUBTYPE_SH7785
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default "0xfffe8000" if CPU_SUBTYPE_SH7203
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default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
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default "0xf8420000" if CPU_SUBTYPE_SH7619
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default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
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default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
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default "0xffc30000" if CPU_SUBTYPE_SHX3
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default "0xffe80000" if CPU_SH4
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default "0x00000000"
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config EARLY_PRINTK
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@ -8,6 +8,7 @@ common-y += $(addprefix ../sh2/, ex.o entry.o)
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obj-$(CONFIG_SH_FPU) += fpu.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
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@ -29,6 +29,9 @@ int __init detect_cpu_and_cache_system(void)
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boot_cpu_data.type = CPU_SH7206;
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/* While SH7206 has a DSP.. */
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boot_cpu_data.flags |= CPU_HAS_DSP;
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#elif defined(CONFIG_CPU_SUBTYPE_MXG)
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boot_cpu_data.type = CPU_MXG;
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boot_cpu_data.flags |= CPU_HAS_DSP;
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#endif
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boot_cpu_data.dcache.ways = 4;
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168
arch/sh/kernel/cpu/sh2a/setup-mxg.c
Normal file
168
arch/sh/kernel/cpu/sh2a/setup-mxg.c
Normal file
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@ -0,0 +1,168 @@
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/*
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* Renesas MX-G (R8A03022BG) Setup
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*
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* Copyright (C) 2008 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
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SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
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SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
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MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
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MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
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MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
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MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
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MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
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MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
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MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
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/* interrupt groups */
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PINT, SCIF0, SCIF1,
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MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
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INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
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INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
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INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
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INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
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INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
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INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
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INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221),
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INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223),
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INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225),
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INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227),
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INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229),
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INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231),
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INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233),
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INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235),
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INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237),
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INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239),
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INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241),
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INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243),
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INTC_IRQ(MTU2_TGI3B, 244),
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INTC_IRQ(MTU2_TGI3C, 245),
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INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247),
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INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249),
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INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251),
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INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253),
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INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
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MTU2_TCI0V, MTU2_TGI0E),
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INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B,
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MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A),
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INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
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MTU2_TGI3A),
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INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A,
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MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
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INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
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INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } },
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{ 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } },
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{ 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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{ 0xfffd9800, 0, 16, 4, /* IPR06 */ { } },
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{ 0xfffd9802, 0, 16, 4, /* IPR07 */ { } },
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{ 0xfffd9804, 0, 16, 4, /* IPR08 */ { } },
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{ 0xfffd9806, 0, 16, 4, /* IPR09 */ { } },
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{ 0xfffd9808, 0, 16, 4, /* IPR10 */ { } },
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{ 0xfffd980a, 0, 16, 4, /* IPR11 */ { } },
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{ 0xfffd980c, 0, 16, 4, /* IPR12 */ { } },
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{ 0xfffd980e, 0, 16, 4, /* IPR13 */ { } },
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{ 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } },
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{ 0xfffd9812, 0, 16, 4, /* IPR15 */
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{ SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
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{ 0xfffd9814, 0, 16, 4, /* IPR16 */
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{ MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfffd9408, 0, 16, /* PINTER */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
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mask_registers, prio_registers, NULL);
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xff804000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 223, 220, 221, 222 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct platform_device *mxg_devices[] __initdata = {
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&sci_device,
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};
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static int __init mxg_devices_setup(void)
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{
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return platform_add_devices(mxg_devices,
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ARRAY_SIZE(mxg_devices));
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}
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__initcall(mxg_devices_setup);
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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}
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@ -335,6 +335,7 @@ static const char *cpu_name[] = {
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[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
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[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
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[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
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[CPU_MXG] = "MX-G",
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[CPU_SH7366] = "SH7366", [CPU_SH_NONE] = "Unknown"
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};
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@ -25,7 +25,7 @@ static void __init check_bugs(void)
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case CPU_SH7619:
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*p++ = '2';
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break;
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case CPU_SH7203 ... CPU_SH7263:
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case CPU_SH7203 ... CPU_MXG:
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*p++ = '2';
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*p++ = 'a';
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break;
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@ -16,7 +16,7 @@ enum cpu_type {
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CPU_SH7619,
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/* SH-2A types */
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CPU_SH7203, CPU_SH7206, CPU_SH7263,
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CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
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/* SH-3 types */
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CPU_SH7705, CPU_SH7706, CPU_SH7707,
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