forked from luck/tmp_suning_uos_patched
i40e: Fix dropped jumbo frames statistics
[ Upstream commit 1adb1563e7b7ec659379a18e607e8bc3522d8a78 ]
Dropped packets caused by too large frames were not included in
dropped RX packets statistics.
Issue was caused by not reading the GL_RXERR1 register. That register
stores count of packet which was have been dropped due to too large
size.
Fix it by reading GL_RXERR1 register for each interface.
Repro steps:
Send a packet larger than the set MTU to SUT
Observe rx statists: ethtool -S <interface> | grep rx | grep -v ": 0"
Fixes: 41a9e55c89 ("i40e: add missing VSI statistics")
Signed-off-by: Lukasz Cieplicki <lukaszx.cieplicki@intel.com>
Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>
Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Lukasz Cieplicki
Greg Kroah-Hartman
parent
5561bddd05
commit
2b4659c145
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@ -37,6 +37,7 @@
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#include <net/tc_act/tc_mirred.h>
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#include <net/udp_tunnel.h>
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#include <net/xdp_sock.h>
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#include <linux/bitfield.h>
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#include "i40e_type.h"
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#include "i40e_prototype.h"
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#include <linux/net/intel/i40e_client.h>
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@ -991,6 +992,21 @@ static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
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(u32)(val & 0xFFFFFFFFULL));
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}
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/**
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* i40e_get_pf_count - get PCI PF count.
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* @hw: pointer to a hw.
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*
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* Reports the function number of the highest PCI physical
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* function plus 1 as it is loaded from the NVM.
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*
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* Return: PCI PF count.
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**/
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static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
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{
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return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
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rd32(hw, I40E_GLGEN_PCIFCNCNT));
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}
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/* needed by i40e_ethtool.c */
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int i40e_up(struct i40e_vsi *vsi);
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void i40e_down(struct i40e_vsi *vsi);
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@ -548,6 +548,47 @@ void i40e_pf_reset_stats(struct i40e_pf *pf)
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pf->hw_csum_rx_error = 0;
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}
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/**
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* i40e_compute_pci_to_hw_id - compute index form PCI function.
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* @vsi: ptr to the VSI to read from.
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* @hw: ptr to the hardware info.
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**/
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static u32 i40e_compute_pci_to_hw_id(struct i40e_vsi *vsi, struct i40e_hw *hw)
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{
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int pf_count = i40e_get_pf_count(hw);
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if (vsi->type == I40E_VSI_SRIOV)
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return (hw->port * BIT(7)) / pf_count + vsi->vf_id;
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return hw->port + BIT(7);
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}
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/**
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* i40e_stat_update64 - read and update a 64 bit stat from the chip.
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* @hw: ptr to the hardware info.
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* @hireg: the high 32 bit reg to read.
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* @loreg: the low 32 bit reg to read.
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* @offset_loaded: has the initial offset been loaded yet.
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* @offset: ptr to current offset value.
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* @stat: ptr to the stat.
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*
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* Since the device stats are not reset at PFReset, they will not
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* be zeroed when the driver starts. We'll save the first values read
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* and use them as offsets to be subtracted from the raw values in order
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* to report stats that count from zero.
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**/
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static void i40e_stat_update64(struct i40e_hw *hw, u32 hireg, u32 loreg,
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bool offset_loaded, u64 *offset, u64 *stat)
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{
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u64 new_data;
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new_data = rd64(hw, loreg);
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if (!offset_loaded || new_data < *offset)
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*offset = new_data;
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*stat = new_data - *offset;
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}
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/**
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* i40e_stat_update48 - read and update a 48 bit stat from the chip
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* @hw: ptr to the hardware info
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@ -619,6 +660,34 @@ static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat)
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*stat += new_data;
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}
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/**
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* i40e_stats_update_rx_discards - update rx_discards.
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* @vsi: ptr to the VSI to be updated.
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* @hw: ptr to the hardware info.
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* @stat_idx: VSI's stat_counter_idx.
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* @offset_loaded: ptr to the VSI's stat_offsets_loaded.
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* @stat_offset: ptr to stat_offset to store first read of specific register.
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* @stat: ptr to VSI's stat to be updated.
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**/
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static void
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i40e_stats_update_rx_discards(struct i40e_vsi *vsi, struct i40e_hw *hw,
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int stat_idx, bool offset_loaded,
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struct i40e_eth_stats *stat_offset,
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struct i40e_eth_stats *stat)
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{
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u64 rx_rdpc, rx_rxerr;
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i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), offset_loaded,
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&stat_offset->rx_discards, &rx_rdpc);
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i40e_stat_update64(hw,
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I40E_GL_RXERR1H(i40e_compute_pci_to_hw_id(vsi, hw)),
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I40E_GL_RXERR1L(i40e_compute_pci_to_hw_id(vsi, hw)),
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offset_loaded, &stat_offset->rx_discards_other,
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&rx_rxerr);
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stat->rx_discards = rx_rdpc + rx_rxerr;
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}
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/**
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* i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
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* @vsi: the VSI to be updated
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@ -678,6 +747,10 @@ void i40e_update_eth_stats(struct i40e_vsi *vsi)
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I40E_GLV_BPTCL(stat_idx),
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vsi->stat_offsets_loaded,
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&oes->tx_broadcast, &es->tx_broadcast);
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i40e_stats_update_rx_discards(vsi, hw, stat_idx,
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vsi->stat_offsets_loaded, oes, es);
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vsi->stat_offsets_loaded = true;
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}
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@ -77,6 +77,11 @@
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#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
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#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
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#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
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#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */
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#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
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#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
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#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
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#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
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#define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */
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#define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0
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#define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
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@ -461,6 +466,14 @@
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#define I40E_VFQF_HKEY1_MAX_INDEX 12
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#define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */
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#define I40E_VFQF_HLUT1_MAX_INDEX 15
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#define I40E_GL_RXERR1H(_i) (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
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#define I40E_GL_RXERR1H_MAX_INDEX 143
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#define I40E_GL_RXERR1H_RXERR1H_SHIFT 0
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#define I40E_GL_RXERR1H_RXERR1H_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT)
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#define I40E_GL_RXERR1L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
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#define I40E_GL_RXERR1L_MAX_INDEX 143
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#define I40E_GL_RXERR1L_RXERR1L_SHIFT 0
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#define I40E_GL_RXERR1L_RXERR1L_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT)
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#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
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@ -1172,6 +1172,7 @@ struct i40e_eth_stats {
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u64 tx_broadcast; /* bptc */
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u64 tx_discards; /* tdpc */
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u64 tx_errors; /* tepc */
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u64 rx_discards_other; /* rxerr1 */
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};
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/* Statistics collected per VEB per TC */
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