forked from luck/tmp_suning_uos_patched
r8169: TSO fixes.
- the MSS value is actually contained in a 11 bits wide (0x7ff) field.
The extra bit in the former MSSMask did encompass the TSO command
bit ("LargeSend") as well (0xfff). Oops.
- the Tx descriptor layout is not the same through the whole chipset
family. The 8169 documentation, the 8168c documentation and Realtek's
drivers (8.020.00, 1.019.00, 6.014.00) highlight two layouts:
1. 8169, 8168 up to 8168b (included) and 8101
2. {8102e, 8168c} and beyond
- notwithstanding the "first descriptor" and "last descriptor" bits, the
same Tx descriptor content is enforced when a packet consists of several
descriptors. The chipsets are documented to require it.
Credits go to David Dillow <dave@thedillows.org> for the original patch.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Cc: Realtek <nic_swsd@realtek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Francois Romieu
David S. Miller
parent
47c2cdf551
commit
2b7b431858
@ -134,47 +134,52 @@ enum mac_version {
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RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
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};
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#define _R(NAME,MAC,MASK) \
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{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
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enum rtl_tx_desc_version {
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RTL_TD_0 = 0,
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RTL_TD_1 = 1,
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};
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#define _R(NAME,MAC,TD) \
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{ .name = NAME, .mac_version = MAC, .txd_version = TD }
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static const struct {
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const char *name;
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u8 mac_version;
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u32 RxConfigMask; /* Clears the bits supported by this chip */
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enum rtl_tx_desc_version txd_version;
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} rtl_chip_info[] = {
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_R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
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_R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
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_R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
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_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
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_R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
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_R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
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_R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
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_R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
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_R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
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_R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
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_R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
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_R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
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_R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880), // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, 0xff7e1880), // PCI-E
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_R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, 0xff7e1880), // PCI-E
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_R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, 0xff7e1880) // PCI-E
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_R("RTL8169", RTL_GIGA_MAC_VER_01, RTL_TD_0), // 8169
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_R("RTL8169s", RTL_GIGA_MAC_VER_02, RTL_TD_0), // 8169S
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_R("RTL8110s", RTL_GIGA_MAC_VER_03, RTL_TD_0), // 8110S
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_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, RTL_TD_0), // 8169SB
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, RTL_TD_0), // 8110SCd
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_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, RTL_TD_0), // 8110SCe
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_R("RTL8102e", RTL_GIGA_MAC_VER_07, RTL_TD_1), // PCI-E
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_R("RTL8102e", RTL_GIGA_MAC_VER_08, RTL_TD_1), // PCI-E
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_R("RTL8102e", RTL_GIGA_MAC_VER_09, RTL_TD_1), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_10, RTL_TD_0), // PCI-E
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, RTL_TD_0), // PCI-E
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, RTL_TD_0), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_13, RTL_TD_0), // PCI-E 8139
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_R("RTL8100e", RTL_GIGA_MAC_VER_14, RTL_TD_0), // PCI-E 8139
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_R("RTL8100e", RTL_GIGA_MAC_VER_15, RTL_TD_0), // PCI-E 8139
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_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, RTL_TD_0), // PCI-E
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_R("RTL8101e", RTL_GIGA_MAC_VER_16, RTL_TD_0), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, RTL_TD_1), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, RTL_TD_1), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, RTL_TD_1), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, RTL_TD_1), // PCI-E
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_R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, RTL_TD_1), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, RTL_TD_1), // PCI-E
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_R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, RTL_TD_1), // PCI-E
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_R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, RTL_TD_1), // PCI-E
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_R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, RTL_TD_1), // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, RTL_TD_1), // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, RTL_TD_1), // PCI-E
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_R("RTL8105e", RTL_GIGA_MAC_VER_29, RTL_TD_1), // PCI-E
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_R("RTL8105e", RTL_GIGA_MAC_VER_30, RTL_TD_1), // PCI-E
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_R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, RTL_TD_1), // PCI-E
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_R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, RTL_TD_1), // PCI-E
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_R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, RTL_TD_1) // PCI-E
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};
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#undef _R
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@ -230,6 +235,9 @@ enum rtl_registers {
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IntrStatus = 0x3e,
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TxConfig = 0x40,
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RxConfig = 0x44,
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#define RTL_RX_CONFIG_MASK 0xff7e1880u
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RxMissed = 0x4c,
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Cfg9346 = 0x50,
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Config0 = 0x51,
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@ -452,21 +460,69 @@ enum rtl_register_content {
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CounterDump = 0x8,
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};
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enum desc_status_bit {
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enum rtl_desc_bit {
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/* First doubleword. */
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DescOwn = (1 << 31), /* Descriptor is owned by NIC */
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RingEnd = (1 << 30), /* End of descriptor ring */
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FirstFrag = (1 << 29), /* First segment of a packet */
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LastFrag = (1 << 28), /* Final segment of a packet */
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};
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/* Tx private */
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LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
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MSSShift = 16, /* MSS value position */
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MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
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IPCS = (1 << 18), /* Calculate IP checksum */
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UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
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TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
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/* Generic case. */
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enum rtl_tx_desc_bit {
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/* First doubleword. */
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TD_LSO = (1 << 27), /* Large Send Offload */
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#define TD_MSS_MAX 0x07ffu /* MSS value */
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/* Second doubleword. */
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TxVlanTag = (1 << 17), /* Add VLAN tag */
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};
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/* 8169, 8168b and 810x except 8102e. */
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enum rtl_tx_desc_bit_0 {
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/* First doubleword. */
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#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
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TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
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TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
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TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
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};
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/* 8102e, 8168c and beyond. */
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enum rtl_tx_desc_bit_1 {
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/* Second doubleword. */
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#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
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TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
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TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
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TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
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};
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static const struct rtl_tx_desc_info {
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struct {
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u32 udp;
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u32 tcp;
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} checksum;
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u16 mss_shift;
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u16 opts_offset;
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} tx_desc_info [] = {
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[RTL_TD_0] = {
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.checksum = {
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.udp = TD0_IP_CS | TD0_UDP_CS,
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.tcp = TD0_IP_CS | TD0_TCP_CS
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},
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.mss_shift = TD0_MSS_SHIFT,
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.opts_offset = 0
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},
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[RTL_TD_1] = {
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.checksum = {
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.udp = TD1_IP_CS | TD1_UDP_CS,
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.tcp = TD1_IP_CS | TD1_TCP_CS
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},
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.mss_shift = TD1_MSS_SHIFT,
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.opts_offset = 1
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}
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};
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enum rtl_rx_desc_bit {
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/* Rx private */
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PID1 = (1 << 18), /* Protocol ID bit 1/2 */
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PID0 = (1 << 17), /* Protocol ID bit 2/2 */
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@ -531,8 +587,8 @@ struct rtl8169_private {
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struct napi_struct napi;
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spinlock_t lock; /* spin lock flag */
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u32 msg_enable;
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int chipset;
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int mac_version;
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u16 txd_version;
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u16 mac_version;
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u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
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u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
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u32 dirty_rx;
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@ -1288,7 +1344,7 @@ static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
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{
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if (dev->mtu > MSSMask)
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if (dev->mtu > TD_MSS_MAX)
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features &= ~NETIF_F_ALL_TSO;
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return features;
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@ -3194,7 +3250,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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struct mii_if_info *mii;
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struct net_device *dev;
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void __iomem *ioaddr;
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unsigned int i;
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int chipset, i;
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int rc;
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if (netif_msg_drv(&debug)) {
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@ -3336,7 +3392,8 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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"driver bug, MAC version not found in rtl_chip_info\n");
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goto err_out_msi_4;
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}
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tp->chipset = i;
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chipset = i;
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tp->txd_version = rtl_chip_info[chipset].txd_version;
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RTL_W8(Cfg9346, Cfg9346_Unlock);
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RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
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@ -3413,8 +3470,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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pci_set_drvdata(pdev, dev);
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netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
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rtl_chip_info[tp->chipset].name,
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dev->base_addr, dev->dev_addr,
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rtl_chip_info[chipset].name, dev->base_addr, dev->dev_addr,
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(u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
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if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
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@ -3572,7 +3628,7 @@ static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
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void __iomem *ioaddr = tp->mmio_addr;
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u32 cfg = rtl8169_rx_config;
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cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
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cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
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RTL_W32(RxConfig, cfg);
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/* Set DMA burst size and Interframe Gap Time */
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@ -4564,7 +4620,7 @@ static void rtl8169_tx_timeout(struct net_device *dev)
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}
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static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
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u32 opts1)
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u32 *opts)
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{
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struct skb_shared_info *info = skb_shinfo(skb);
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unsigned int cur_frag, entry;
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@ -4592,9 +4648,11 @@ static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
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}
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/* anti gcc 2.95.3 bugware (sic) */
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status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
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status = opts[0] | len |
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(RingEnd * !((entry + 1) % NUM_TX_DESC));
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txd->opts1 = cpu_to_le32(status);
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txd->opts2 = cpu_to_le32(opts[1]);
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txd->addr = cpu_to_le64(mapping);
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tp->tx_skb[entry].len = len;
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@ -4612,23 +4670,26 @@ static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
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return -EIO;
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}
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static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
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static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
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struct sk_buff *skb, u32 *opts)
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{
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const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
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u32 mss = skb_shinfo(skb)->gso_size;
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int offset = info->opts_offset;
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if (mss)
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return LargeSend | ((mss & MSSMask) << MSSShift);
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if (skb->ip_summed == CHECKSUM_PARTIAL) {
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if (mss) {
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opts[0] |= TD_LSO;
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opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
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} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
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const struct iphdr *ip = ip_hdr(skb);
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if (ip->protocol == IPPROTO_TCP)
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return IPCS | TCPCS;
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opts[offset] |= info->checksum.tcp;
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else if (ip->protocol == IPPROTO_UDP)
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return IPCS | UDPCS;
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WARN_ON(1); /* we need a WARN() */
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opts[offset] |= info->checksum.udp;
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else
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WARN_ON_ONCE(1);
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}
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return 0;
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}
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static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
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@ -4641,7 +4702,7 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
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struct device *d = &tp->pci_dev->dev;
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dma_addr_t mapping;
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u32 status, len;
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u32 opts1;
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u32 opts[2];
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int frags;
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if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
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@ -4662,24 +4723,28 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
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tp->tx_skb[entry].len = len;
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txd->addr = cpu_to_le64(mapping);
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txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
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opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
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opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
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opts[0] = DescOwn;
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|
||||
frags = rtl8169_xmit_frags(tp, skb, opts1);
|
||||
rtl8169_tso_csum(tp, skb, opts);
|
||||
|
||||
frags = rtl8169_xmit_frags(tp, skb, opts);
|
||||
if (frags < 0)
|
||||
goto err_dma_1;
|
||||
else if (frags)
|
||||
opts1 |= FirstFrag;
|
||||
opts[0] |= FirstFrag;
|
||||
else {
|
||||
opts1 |= FirstFrag | LastFrag;
|
||||
opts[0] |= FirstFrag | LastFrag;
|
||||
tp->tx_skb[entry].skb = skb;
|
||||
}
|
||||
|
||||
txd->opts2 = cpu_to_le32(opts[1]);
|
||||
|
||||
wmb();
|
||||
|
||||
/* anti gcc 2.95.3 bugware (sic) */
|
||||
status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
|
||||
status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
|
||||
txd->opts1 = cpu_to_le32(status);
|
||||
|
||||
tp->cur_tx += frags + 1;
|
||||
@ -5167,7 +5232,7 @@ static void rtl_set_rx_mode(struct net_device *dev)
|
||||
spin_lock_irqsave(&tp->lock, flags);
|
||||
|
||||
tmp = rtl8169_rx_config | rx_mode |
|
||||
(RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
|
||||
(RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
|
||||
|
||||
if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
|
||||
u32 data = mc_filter[0];
|
||||
|
||||
Loading…
Reference in New Issue
Block a user