forked from luck/tmp_suning_uos_patched
i2c: xlp9xx: Driver for Netlogic XLP9XX/5XX I2C controller
Add an I2C bus driver i2c-xlp9xx.c to support the I2C block in the XLP9xx/XLP5xx MIPS SoC. Update Kconfig and Makefile to add the CONFIG_I2C_XLP9XX option. Signed-off-by: Subhendu Sekhar Behera <sbehera@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Subhendu Sekhar Behera
Wolfram Sang
parent
85e4564ab2
commit
2bbd681ba2
22
Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt
Normal file
22
Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt
Normal file
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@ -0,0 +1,22 @@
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Device tree configuration for the I2C controller on the XLP9xx/5xx SoC
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Required properties:
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- compatible : should be "netlogic,xlp980-i2c"
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- reg : bus address start and address range size of device
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- interrupts : interrupt number
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Optional properties:
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- clock-frequency : frequency of bus clock in Hz
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Defaults to 100 KHz when the property is not specified
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Example:
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i2c0: i2c@113100 {
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compatible = "netlogic,xlp980-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x113100 0x100>;
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clock-frequency = <400000>;
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interrupts = <30>;
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interrupt-parent = <&pic>;
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};
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@ -916,6 +916,16 @@ config I2C_XLR
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This driver can also be built as a module. If so, the module
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will be called i2c-xlr.
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config I2C_XLP9XX
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tristate "XLP9XX I2C support"
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depends on CPU_XLP || COMPILE_TEST
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help
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This driver enables support for the on-chip I2C interface of
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the Broadcom XLP9xx/XLP5xx MIPS processors.
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This driver can also be built as a module. If so, the module will
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be called i2c-xlp9xx.
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config I2C_RCAR
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tristate "Renesas R-Car I2C Controller"
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depends on ARCH_SHMOBILE || COMPILE_TEST
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@ -89,6 +89,7 @@ obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
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obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
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obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
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obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
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obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
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obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
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# External I2C/SMBus adapter drivers
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445
drivers/i2c/busses/i2c-xlp9xx.c
Normal file
445
drivers/i2c/busses/i2c-xlp9xx.c
Normal file
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@ -0,0 +1,445 @@
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/*
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* Copyright (c) 2003-2015 Broadcom Corporation
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/completion.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define XLP9XX_I2C_DIV 0x0
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#define XLP9XX_I2C_CTRL 0x1
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#define XLP9XX_I2C_CMD 0x2
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#define XLP9XX_I2C_STATUS 0x3
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#define XLP9XX_I2C_MTXFIFO 0x4
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#define XLP9XX_I2C_MRXFIFO 0x5
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#define XLP9XX_I2C_MFIFOCTRL 0x6
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#define XLP9XX_I2C_STXFIFO 0x7
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#define XLP9XX_I2C_SRXFIFO 0x8
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#define XLP9XX_I2C_SFIFOCTRL 0x9
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#define XLP9XX_I2C_SLAVEADDR 0xA
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#define XLP9XX_I2C_OWNADDR 0xB
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#define XLP9XX_I2C_FIFOWCNT 0xC
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#define XLP9XX_I2C_INTEN 0xD
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#define XLP9XX_I2C_INTST 0xE
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#define XLP9XX_I2C_WAITCNT 0xF
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#define XLP9XX_I2C_TIMEOUT 0X10
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#define XLP9XX_I2C_GENCALLADDR 0x11
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#define XLP9XX_I2C_CMD_START BIT(7)
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#define XLP9XX_I2C_CMD_STOP BIT(6)
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#define XLP9XX_I2C_CMD_READ BIT(5)
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#define XLP9XX_I2C_CMD_WRITE BIT(4)
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#define XLP9XX_I2C_CMD_ACK BIT(3)
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#define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16
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#define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000
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#define XLP9XX_I2C_CTRL_RST BIT(8)
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#define XLP9XX_I2C_CTRL_EN BIT(6)
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#define XLP9XX_I2C_CTRL_MASTER BIT(4)
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#define XLP9XX_I2C_CTRL_FIFORD BIT(1)
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#define XLP9XX_I2C_CTRL_ADDMODE BIT(0)
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#define XLP9XX_I2C_INTEN_NACKADDR BIT(25)
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#define XLP9XX_I2C_INTEN_SADDR BIT(13)
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#define XLP9XX_I2C_INTEN_DATADONE BIT(12)
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#define XLP9XX_I2C_INTEN_ARLOST BIT(11)
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#define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4)
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#define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3)
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#define XLP9XX_I2C_INTEN_MFIFOHI BIT(2)
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#define XLP9XX_I2C_INTEN_BUSERR BIT(0)
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#define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8
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#define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0
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#define XLP9XX_I2C_MFIFOCTRL_RST BIT(16)
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#define XLP9XX_I2C_SLAVEADDR_RW BIT(0)
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#define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1
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#define XLP9XX_I2C_IP_CLK_FREQ 133000000UL
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#define XLP9XX_I2C_DEFAULT_FREQ 100000
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#define XLP9XX_I2C_HIGH_FREQ 400000
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#define XLP9XX_I2C_FIFO_SIZE 0x80U
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#define XLP9XX_I2C_TIMEOUT_MS 1000
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#define XLP9XX_I2C_FIFO_WCNT_MASK 0xff
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#define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST | \
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XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR)
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struct xlp9xx_i2c_dev {
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struct device *dev;
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struct i2c_adapter adapter;
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struct completion msg_complete;
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int irq;
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bool msg_read;
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u32 __iomem *base;
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u32 msg_buf_remaining;
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u32 msg_len;
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u32 clk_hz;
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u32 msg_err;
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u8 *msg_buf;
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};
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static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv,
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unsigned long reg, u32 val)
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{
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writel(val, priv->base + reg);
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}
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static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv,
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unsigned long reg)
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{
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return readl(priv->base + reg);
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}
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static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
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{
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u32 inten;
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inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
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}
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static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
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{
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u32 inten;
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inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
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}
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static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv)
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{
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u32 thres;
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thres = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
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thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT);
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}
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static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv)
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{
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u32 len, i;
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u8 *buf = priv->msg_buf;
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len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
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for (i = 0; i < len; i++)
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]);
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priv->msg_buf_remaining -= len;
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priv->msg_buf += len;
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}
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static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv)
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{
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u32 len, i;
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u8 *buf = priv->msg_buf;
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len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
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XLP9XX_I2C_FIFO_WCNT_MASK;
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len = min(priv->msg_buf_remaining, len);
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for (i = 0; i < len; i++, buf++)
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*buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
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priv->msg_buf_remaining -= len;
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priv->msg_buf = buf;
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if (priv->msg_buf_remaining)
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xlp9xx_i2c_update_rx_fifo_thres(priv);
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}
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static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id)
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{
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struct xlp9xx_i2c_dev *priv = dev_id;
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u32 status;
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status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST);
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if (status == 0)
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return IRQ_NONE;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status);
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if (status & XLP9XX_I2C_STATUS_ERRMASK) {
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priv->msg_err = status;
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goto xfer_done;
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}
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/* SADDR ACK for SMBUS_QUICK */
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if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0))
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goto xfer_done;
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if (!priv->msg_read) {
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if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) {
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/* TX FIFO got empty, fill it up again */
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if (priv->msg_buf_remaining)
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xlp9xx_i2c_fill_tx_fifo(priv);
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else
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xlp9xx_i2c_mask_irq(priv,
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XLP9XX_I2C_INTEN_MFIFOEMTY);
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}
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} else {
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if (status & (XLP9XX_I2C_INTEN_DATADONE |
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XLP9XX_I2C_INTEN_MFIFOHI)) {
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/* data is in FIFO, read it */
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if (priv->msg_buf_remaining)
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xlp9xx_i2c_drain_rx_fifo(priv);
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}
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}
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/* Transfer complete */
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if (status & XLP9XX_I2C_INTEN_DATADONE)
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goto xfer_done;
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return IRQ_HANDLED;
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xfer_done:
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
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complete(&priv->msg_complete);
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return IRQ_HANDLED;
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}
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static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv)
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{
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u32 prescale;
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/*
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* The controller uses 5 * SCL clock internally.
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* So prescale value should be divided by 5.
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*/
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prescale = DIV_ROUND_UP(XLP9XX_I2C_IP_CLK_FREQ, priv->clk_hz);
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prescale = ((prescale - 8) / 5) - 1;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN |
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XLP9XX_I2C_CTRL_MASTER);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
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return 0;
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}
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static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg,
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int last_msg)
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{
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unsigned long timeleft;
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u32 intr_mask, cmd, val;
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priv->msg_buf = msg->buf;
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priv->msg_buf_remaining = priv->msg_len = msg->len;
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priv->msg_err = 0;
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priv->msg_read = (msg->flags & I2C_M_RD);
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reinit_completion(&priv->msg_complete);
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/* Reset FIFO */
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
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XLP9XX_I2C_MFIFOCTRL_RST);
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/* set FIFO threshold if reading */
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if (priv->msg_read)
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xlp9xx_i2c_update_rx_fifo_thres(priv);
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/* set slave addr */
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR,
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(msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) |
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(priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0));
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/* Build control word for transfer */
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val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
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if (!priv->msg_read)
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val &= ~XLP9XX_I2C_CTRL_FIFORD;
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else
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val |= XLP9XX_I2C_CTRL_FIFORD; /* read */
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if (msg->flags & I2C_M_TEN)
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val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/
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else
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val &= ~XLP9XX_I2C_CTRL_ADDMODE;
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/* set data length to be transferred */
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val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
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(msg->len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
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/* fill fifo during tx */
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if (!priv->msg_read)
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xlp9xx_i2c_fill_tx_fifo(priv);
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/* set interrupt mask */
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intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR |
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XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE);
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if (priv->msg_read) {
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intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI;
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if (msg->len == 0)
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intr_mask |= XLP9XX_I2C_INTEN_SADDR;
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} else {
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if (msg->len == 0)
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intr_mask |= XLP9XX_I2C_INTEN_SADDR;
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else
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intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY;
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}
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xlp9xx_i2c_unmask_irq(priv, intr_mask);
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/* set cmd reg */
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cmd = XLP9XX_I2C_CMD_START;
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cmd |= (priv->msg_read ? XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE);
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if (last_msg)
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cmd |= XLP9XX_I2C_CMD_STOP;
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xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd);
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timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS);
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timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft);
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if (priv->msg_err) {
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dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err);
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if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR)
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xlp9xx_i2c_init(priv);
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return -EIO;
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}
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if (timeleft == 0) {
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dev_dbg(priv->dev, "i2c transfer timed out!\n");
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xlp9xx_i2c_init(priv);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num)
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{
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int i, ret;
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struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap);
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for (i = 0; i < num; i++) {
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ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1);
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if (ret != 0)
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return ret;
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}
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return num;
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}
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static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C |
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I2C_FUNC_10BIT_ADDR;
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}
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|
||||
static struct i2c_algorithm xlp9xx_i2c_algo = {
|
||||
.master_xfer = xlp9xx_i2c_xfer,
|
||||
.functionality = xlp9xx_i2c_functionality,
|
||||
};
|
||||
|
||||
static int xlp9xx_i2c_get_frequency(struct platform_device *pdev,
|
||||
struct xlp9xx_i2c_dev *priv)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
u32 freq;
|
||||
int err;
|
||||
|
||||
err = of_property_read_u32(np, "clock-frequency", &freq);
|
||||
if (err) {
|
||||
freq = XLP9XX_I2C_DEFAULT_FREQ;
|
||||
dev_dbg(&pdev->dev, "using default frequency %u\n", freq);
|
||||
} else if (freq == 0 || freq > XLP9XX_I2C_HIGH_FREQ) {
|
||||
dev_warn(&pdev->dev, "invalid frequency %u, using default\n",
|
||||
freq);
|
||||
freq = XLP9XX_I2C_DEFAULT_FREQ;
|
||||
}
|
||||
priv->clk_hz = freq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xlp9xx_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct xlp9xx_i2c_dev *priv;
|
||||
struct resource *res;
|
||||
int err = 0;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
priv->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
priv->irq = platform_get_irq(pdev, 0);
|
||||
if (priv->irq <= 0) {
|
||||
dev_err(&pdev->dev, "invalid irq!\n");
|
||||
return priv->irq;
|
||||
}
|
||||
|
||||
xlp9xx_i2c_get_frequency(pdev, priv);
|
||||
xlp9xx_i2c_init(priv);
|
||||
|
||||
err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0,
|
||||
pdev->name, priv);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "IRQ request failed!\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
init_completion(&priv->msg_complete);
|
||||
priv->adapter.dev.parent = &pdev->dev;
|
||||
priv->adapter.algo = &xlp9xx_i2c_algo;
|
||||
priv->adapter.dev.of_node = pdev->dev.of_node;
|
||||
priv->dev = &pdev->dev;
|
||||
|
||||
snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c");
|
||||
i2c_set_adapdata(&priv->adapter, priv);
|
||||
|
||||
err = i2c_add_adapter(&priv->adapter);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "failed to add I2C adapter!\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, priv);
|
||||
dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xlp9xx_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct xlp9xx_i2c_dev *priv;
|
||||
|
||||
priv = platform_get_drvdata(pdev);
|
||||
xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
|
||||
synchronize_irq(priv->irq);
|
||||
i2c_del_adapter(&priv->adapter);
|
||||
xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id xlp9xx_i2c_of_match[] = {
|
||||
{ .compatible = "netlogic,xlp980-i2c", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct platform_driver xlp9xx_i2c_driver = {
|
||||
.probe = xlp9xx_i2c_probe,
|
||||
.remove = xlp9xx_i2c_remove,
|
||||
.driver = {
|
||||
.name = "xlp9xx-i2c",
|
||||
.of_match_table = xlp9xx_i2c_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(xlp9xx_i2c_driver);
|
||||
|
||||
MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>");
|
||||
MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user