[SCSI] hpsa: do not read from controller unnecessarily in completion code

MSI/MSI-X interrupts can't race the DMA completion they are communicating
so no need to read from controller to flush the DMA to the host if
MSI or MSI-X interrupts are being used.

Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Stephen M. Cameron 2012-05-01 11:42:30 -05:00 committed by James Bottomley
parent 21b8e4ef03
commit 2c17d2da8c

View File

@ -258,12 +258,12 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h)
{ {
unsigned long register_value = FIFO_EMPTY; unsigned long register_value = FIFO_EMPTY;
/* flush the controller write of the reply queue by reading
* outbound doorbell status register.
*/
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
/* msi auto clears the interrupt pending bit. */ /* msi auto clears the interrupt pending bit. */
if (!(h->msi_vector || h->msix_vector)) { if (!(h->msi_vector || h->msix_vector)) {
/* flush the controller write of the reply queue by reading
* outbound doorbell status register.
*/
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
/* Do a read in order to flush the write to the controller /* Do a read in order to flush the write to the controller
* (as per spec.) * (as per spec.)