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video: exynos_dp: Fix incorrect setting for INT_CTL

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INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL.
This patch fixes the wrong register setting for INT_CTL.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
This commit is contained in:
Ajay Kumar 2012-11-05 16:47:00 +09:00 committed by Jingoo Han
parent 22ce19cb43
commit 2f85f97e46
2 changed files with 3 additions and 2 deletions
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2
drivers/video/exynos/exynos_dp_reg.c
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@ -88,7 +88,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
void exynos_dp_init_interrupt(struct exynos_dp_device *dp) void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
{ {
/* Set interrupt pin assertion polarity as high */ /* Set interrupt pin assertion polarity as high */
writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL); writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
/* Clear pending regisers */ /* Clear pending regisers */
writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);

3
drivers/video/exynos/exynos_dp_reg.h
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@ -242,7 +242,8 @@
/* EXYNOS_DP_INT_CTL */ /* EXYNOS_DP_INT_CTL */
#define SOFT_INT_CTRL (0x1 << 2) #define SOFT_INT_CTRL (0x1 << 2)
#define INT_POL (0x1 << 0) #define INT_POL1 (0x1 << 1)
#define INT_POL0 (0x1 << 0)
/* EXYNOS_DP_SYS_CTL_1 */ /* EXYNOS_DP_SYS_CTL_1 */
#define DET_STA (0x1 << 2) #define DET_STA (0x1 << 2)