forked from luck/tmp_suning_uos_patched
ARM: 7389/2: plat-versatile: modernize FPGA IRQ controller
This does two things to the FPGA IRQ controller in the versatile family: - Convert to MULTI_IRQ_HANDLER so we can drop the entry macro from the Integrator. The C IRQ handler was inspired from arch/arm/common/vic.c, recent bug discovered in this handler was accounted for. - Convert to using IRQ domains so we can get rid of the NO_IRQ mess and proceed with device tree and such stuff. As part of the exercise, bump all the low IRQ numbers on the Integrator PIC to start from 1 rather than 0, since IRQ 0 is now NO_IRQ. The Linux IRQ numbers are thus entirely decoupled from the hardware IRQ numbers in this controller. I was unable to split this patch. The main reason is the half-done conversion to device tree in Versatile. Tested on Integrator/AP and Integrator/CP. Cc: Grant Likely <grant.likely@secretlab.ca> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Linus Walleij
Russell King
parent
69964ea4c7
commit
3108e6ab21
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@ -280,6 +280,7 @@ config ARCH_INTEGRATOR
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select NEED_MACH_IO_H
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select NEED_MACH_MEMORY_H
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select SPARSE_IRQ
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select MULTI_IRQ_HANDLER
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help
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Support for ARM's Integrator platform.
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@ -1,39 +0,0 @@
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/*
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* arch/arm/mach-integrator/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for Integrator platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <mach/irqs.h>
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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/* FIXME: should not be using soo many LDRs here */
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ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
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mov \irqnr, #IRQ_PIC_START
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ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status
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ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
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teq \irqstat, #0
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ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
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moveq \irqnr, #IRQ_CIC_START
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1001: tst \irqstat, #15
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bne 1002f
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add \irqnr, \irqnr, #4
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movs \irqstat, \irqstat, lsr #4
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bne 1001b
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1002: tst \irqstat, #1
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bne 1003f
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add \irqnr, \irqnr, #1
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movs \irqstat, \irqstat, lsr #1
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bne 1002b
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1003: /* EQ will be set if no irqs pending */
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.endm
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@ -22,37 +22,37 @@
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/*
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* Interrupt numbers
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*/
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#define IRQ_PIC_START 0
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#define IRQ_SOFTINT 0
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#define IRQ_UARTINT0 1
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#define IRQ_UARTINT1 2
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#define IRQ_KMIINT0 3
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#define IRQ_KMIINT1 4
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#define IRQ_TIMERINT0 5
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#define IRQ_TIMERINT1 6
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#define IRQ_TIMERINT2 7
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#define IRQ_RTCINT 8
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#define IRQ_AP_EXPINT0 9
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#define IRQ_AP_EXPINT1 10
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#define IRQ_AP_EXPINT2 11
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#define IRQ_AP_EXPINT3 12
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#define IRQ_AP_PCIINT0 13
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#define IRQ_AP_PCIINT1 14
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#define IRQ_AP_PCIINT2 15
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#define IRQ_AP_PCIINT3 16
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#define IRQ_AP_V3INT 17
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#define IRQ_AP_CPINT0 18
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#define IRQ_AP_CPINT1 19
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#define IRQ_AP_LBUSTIMEOUT 20
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#define IRQ_AP_APCINT 21
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#define IRQ_CP_CLCDCINT 22
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#define IRQ_CP_MMCIINT0 23
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#define IRQ_CP_MMCIINT1 24
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#define IRQ_CP_AACIINT 25
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#define IRQ_CP_CPPLDINT 26
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#define IRQ_CP_ETHINT 27
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#define IRQ_CP_TSPENINT 28
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#define IRQ_PIC_END 31
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#define IRQ_PIC_START 1
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#define IRQ_SOFTINT 1
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#define IRQ_UARTINT0 2
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#define IRQ_UARTINT1 3
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#define IRQ_KMIINT0 4
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#define IRQ_KMIINT1 5
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#define IRQ_TIMERINT0 6
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#define IRQ_TIMERINT1 7
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#define IRQ_TIMERINT2 8
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#define IRQ_RTCINT 9
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#define IRQ_AP_EXPINT0 10
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#define IRQ_AP_EXPINT1 11
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#define IRQ_AP_EXPINT2 12
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#define IRQ_AP_EXPINT3 13
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#define IRQ_AP_PCIINT0 14
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#define IRQ_AP_PCIINT1 15
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#define IRQ_AP_PCIINT2 16
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#define IRQ_AP_PCIINT3 17
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#define IRQ_AP_V3INT 18
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#define IRQ_AP_CPINT0 19
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#define IRQ_AP_CPINT1 20
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#define IRQ_AP_LBUSTIMEOUT 21
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#define IRQ_AP_APCINT 22
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#define IRQ_CP_CLCDCINT 23
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#define IRQ_CP_MMCIINT0 24
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#define IRQ_CP_MMCIINT1 25
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#define IRQ_CP_AACIINT 26
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#define IRQ_CP_CPPLDINT 27
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#define IRQ_CP_ETHINT 28
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#define IRQ_CP_TSPENINT 29
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#define IRQ_PIC_END 29
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#define IRQ_CIC_START 32
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#define IRQ_CM_SOFTINT 32
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@ -80,4 +80,3 @@
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#define NR_IRQS_INTEGRATOR_AP 34
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#define NR_IRQS_INTEGRATOR_CP 47
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@ -162,12 +162,6 @@ static void __init ap_map_io(void)
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#define INTEGRATOR_SC_VALID_INT 0x003fffff
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static struct fpga_irq_data sc_irq_data = {
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.base = VA_IC_BASE,
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.irq_start = 0,
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.chip.name = "SC",
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};
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static void __init ap_init_irq(void)
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{
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/* Disable all interrupts initially. */
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@ -178,7 +172,8 @@ static void __init ap_init_irq(void)
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
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fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
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-1, INTEGRATOR_SC_VALID_INT, NULL);
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}
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#ifdef CONFIG_PM
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@ -478,6 +473,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
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.nr_irqs = NR_IRQS_INTEGRATOR_AP,
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.init_early = integrator_init_early,
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.init_irq = ap_init_irq,
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.handle_irq = fpga_handle_irq,
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.timer = &ap_timer,
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.init_machine = ap_init,
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.restart = integrator_restart,
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@ -143,30 +143,14 @@ static void __init intcp_map_io(void)
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iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
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}
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static struct fpga_irq_data cic_irq_data = {
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.base = INTCP_VA_CIC_BASE,
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.irq_start = IRQ_CIC_START,
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.chip.name = "CIC",
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};
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static struct fpga_irq_data pic_irq_data = {
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.base = INTCP_VA_PIC_BASE,
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.irq_start = IRQ_PIC_START,
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.chip.name = "PIC",
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};
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static struct fpga_irq_data sic_irq_data = {
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.base = INTCP_VA_SIC_BASE,
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.irq_start = IRQ_SIC_START,
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.chip.name = "SIC",
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};
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static void __init intcp_init_irq(void)
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{
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u32 pic_mask, sic_mask;
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u32 pic_mask, cic_mask, sic_mask;
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/* These masks are for the HW IRQ registers */
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pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
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pic_mask |= (~((~0u) << (29 - 22))) << 22;
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cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
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sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
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/*
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@ -179,12 +163,14 @@ static void __init intcp_init_irq(void)
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writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
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writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
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fpga_irq_init(-1, pic_mask, &pic_irq_data);
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fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
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-1, pic_mask, NULL);
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fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)),
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&cic_irq_data);
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fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
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-1, cic_mask, NULL);
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fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data);
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fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
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IRQ_CP_CPPLDINT, sic_mask, NULL);
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}
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/*
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@ -467,6 +453,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
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.nr_irqs = NR_IRQS_INTEGRATOR_CP,
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.init_early = intcp_init_early,
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.init_irq = intcp_init_irq,
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.handle_irq = fpga_handle_irq,
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.timer = &cp_timer,
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.init_machine = intcp_init,
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.restart = integrator_restart,
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@ -66,12 +66,6 @@
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#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
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#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
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static struct fpga_irq_data sic_irq = {
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.base = VA_SIC_BASE,
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.irq_start = IRQ_SIC_START,
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.chip.name = "SIC",
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};
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#if 1
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#define IRQ_MMCI0A IRQ_VICSOURCE22
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#define IRQ_AACI IRQ_VICSOURCE24
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@ -105,8 +99,11 @@ void __init versatile_init_irq(void)
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writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
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fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
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irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START);
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np = of_find_matching_node_by_address(NULL, sic_of_match,
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VERSATILE_SIC_BASE);
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fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
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IRQ_VICSOURCE31, ~PIC_MASK, np);
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/*
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* Interrupts on secondary controller from 0 to 8 are routed to
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@ -5,6 +5,12 @@ config PLAT_VERSATILE_CLCD
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config PLAT_VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config PLAT_VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on PLAT_VERSATILE_FPGA_IRQ
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config PLAT_VERSATILE_LEDS
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def_bool y if LEDS_CLASS
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@ -3,7 +3,10 @@
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*/
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include <plat/fpga-irq.h>
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@ -12,10 +15,32 @@
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#define IRQ_ENABLE_SET 0x08
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#define IRQ_ENABLE_CLEAR 0x0c
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/**
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* struct fpga_irq_data - irq data container for the FPGA IRQ controller
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* @base: memory offset in virtual memory
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* @irq_start: first IRQ number handled by this instance
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* @chip: chip container for this instance
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* @domain: IRQ domain for this instance
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* @valid: mask for valid IRQs on this controller
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* @used_irqs: number of active IRQs on this controller
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*/
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struct fpga_irq_data {
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void __iomem *base;
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unsigned int irq_start;
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struct irq_chip chip;
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u32 valid;
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struct irq_domain *domain;
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u8 used_irqs;
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};
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/* we cannot allocate memory when the controllers are initially registered */
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static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR];
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static int fpga_irq_id;
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static void fpga_irq_mask(struct irq_data *d)
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{
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struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - f->irq_start);
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u32 mask = 1 << d->hwirq;
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writel(mask, f->base + IRQ_ENABLE_CLEAR);
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}
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@ -23,7 +48,7 @@ static void fpga_irq_mask(struct irq_data *d)
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static void fpga_irq_unmask(struct irq_data *d)
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{
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struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - f->irq_start);
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u32 mask = 1 << d->hwirq;
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writel(mask, f->base + IRQ_ENABLE_SET);
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}
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@ -41,32 +66,93 @@ static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
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do {
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irq = ffs(status) - 1;
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status &= ~(1 << irq);
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generic_handle_irq(irq + f->irq_start);
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generic_handle_irq(irq_find_mapping(f->domain, irq));
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} while (status);
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}
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void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f)
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/*
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* Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
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* if we've handled at least one interrupt. This does a single read of the
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* status register and handles all interrupts in order from LSB first.
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*/
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static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
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{
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unsigned int i;
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int handled = 0;
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int irq;
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u32 status;
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while ((status = readl(f->base + IRQ_STATUS))) {
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irq = ffs(status) - 1;
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handle_IRQ(irq_find_mapping(f->domain, irq), regs);
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handled = 1;
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}
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return handled;
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}
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/*
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* Keep iterating over all registered FPGA IRQ controllers until there are
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* no pending interrupts.
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*/
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asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
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{
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int i, handled;
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do {
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for (i = 0, handled = 0; i < fpga_irq_id; ++i)
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handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
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} while (handled);
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}
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static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct fpga_irq_data *f = d->host_data;
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/* Skip invalid IRQs, only register handlers for the real ones */
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if (!(f->valid & (1 << hwirq)))
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return -ENOTSUPP;
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irq_set_chip_data(irq, f);
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irq_set_chip_and_handler(irq, &f->chip,
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handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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f->used_irqs++;
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return 0;
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}
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static struct irq_domain_ops fpga_irqdomain_ops = {
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.map = fpga_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
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int parent_irq, u32 valid, struct device_node *node)
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{
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struct fpga_irq_data *f;
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if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
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printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
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return;
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}
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f = &fpga_irq_devices[fpga_irq_id];
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f->base = base;
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f->irq_start = irq_start;
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f->chip.name = name;
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f->chip.irq_ack = fpga_irq_mask;
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f->chip.irq_mask = fpga_irq_mask;
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f->chip.irq_unmask = fpga_irq_unmask;
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f->valid = valid;
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if (parent_irq != -1) {
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irq_set_handler_data(parent_irq, f);
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irq_set_chained_handler(parent_irq, fpga_irq_handle);
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}
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for (i = 0; i < 32; i++) {
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if (valid & (1 << i)) {
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unsigned int irq = f->irq_start + i;
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f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0,
|
||||
&fpga_irqdomain_ops, f);
|
||||
pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
|
||||
fpga_irq_id, name, base, f->used_irqs);
|
||||
|
||||
irq_set_chip_data(irq, f);
|
||||
irq_set_chip_and_handler(irq, &f->chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
}
|
||||
fpga_irq_id++;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,12 +1,11 @@
|
|||
#ifndef PLAT_FPGA_IRQ_H
|
||||
#define PLAT_FPGA_IRQ_H
|
||||
|
||||
struct fpga_irq_data {
|
||||
void __iomem *base;
|
||||
unsigned int irq_start;
|
||||
struct irq_chip chip;
|
||||
};
|
||||
struct device_node;
|
||||
struct pt_regs;
|
||||
|
||||
void fpga_irq_init(int, u32, struct fpga_irq_data *);
|
||||
void fpga_handle_irq(struct pt_regs *regs);
|
||||
void fpga_irq_init(void __iomem *, const char *, int, int, u32,
|
||||
struct device_node *node);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user