forked from luck/tmp_suning_uos_patched
pci: tegra: use reset framework
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. The old Tegra-specific API used a struct clock to represent the module to reset. Some of the clocks retrieved during probe() were only used for reset purposes, and indeed aren't even true clocks. So, there's no need to get() them any more. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
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@ -25,7 +25,6 @@
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*/
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#include <linux/clk.h>
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#include <linux/clk/tegra.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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@ -39,6 +38,7 @@
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/tegra-cpuidle.h>
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@ -259,10 +259,13 @@ struct tegra_pcie {
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struct clk *pex_clk;
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struct clk *afi_clk;
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struct clk *pcie_xclk;
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struct clk *pll_e;
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struct clk *cml_clk;
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struct reset_control *pex_rst;
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struct reset_control *afi_rst;
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struct reset_control *pcie_xrst;
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struct tegra_msi msi;
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struct list_head ports;
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@ -858,7 +861,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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pads_writel(pcie, value, PADS_CTL);
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/* take the PCIe interface module out of reset */
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tegra_periph_reset_deassert(pcie->pcie_xclk);
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reset_control_deassert(pcie->pcie_xrst);
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/* finally enable PCIe */
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value = afi_readl(pcie, AFI_CONFIGURATION);
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@ -891,9 +894,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
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/* TODO: disable and unprepare clocks? */
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tegra_periph_reset_assert(pcie->pcie_xclk);
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tegra_periph_reset_assert(pcie->afi_clk);
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tegra_periph_reset_assert(pcie->pex_clk);
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reset_control_assert(pcie->pcie_xrst);
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reset_control_assert(pcie->afi_rst);
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reset_control_assert(pcie->pex_rst);
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tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
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@ -921,9 +924,9 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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int err;
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tegra_periph_reset_assert(pcie->pcie_xclk);
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tegra_periph_reset_assert(pcie->afi_clk);
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tegra_periph_reset_assert(pcie->pex_clk);
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reset_control_assert(pcie->pcie_xrst);
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reset_control_assert(pcie->afi_rst);
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reset_control_assert(pcie->pex_rst);
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tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
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@ -958,7 +961,7 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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return err;
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}
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tegra_periph_reset_deassert(pcie->afi_clk);
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reset_control_deassert(pcie->afi_rst);
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err = clk_prepare_enable(pcie->afi_clk);
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if (err < 0) {
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@ -996,10 +999,6 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
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if (IS_ERR(pcie->afi_clk))
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return PTR_ERR(pcie->afi_clk);
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pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk");
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if (IS_ERR(pcie->pcie_xclk))
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return PTR_ERR(pcie->pcie_xclk);
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pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
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if (IS_ERR(pcie->pll_e))
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return PTR_ERR(pcie->pll_e);
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@ -1013,6 +1012,23 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
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return 0;
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}
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static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
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{
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pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
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if (IS_ERR(pcie->pex_rst))
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return PTR_ERR(pcie->pex_rst);
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pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
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if (IS_ERR(pcie->afi_rst))
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return PTR_ERR(pcie->afi_rst);
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pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
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if (IS_ERR(pcie->pcie_xrst))
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return PTR_ERR(pcie->pcie_xrst);
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return 0;
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}
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static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
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{
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struct platform_device *pdev = to_platform_device(pcie->dev);
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@ -1025,6 +1041,12 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
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return err;
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}
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err = tegra_pcie_resets_get(pcie);
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if (err) {
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dev_err(&pdev->dev, "failed to get resets: %d\n", err);
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return err;
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}
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err = tegra_pcie_power_on(pcie);
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if (err) {
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dev_err(&pdev->dev, "failed to power up: %d\n", err);
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