forked from luck/tmp_suning_uos_patched
arch/tile: Fix a couple of issues with the COMPAT code for TILE-Gx.
First, the siginfo preamble wasn't quite right; we need to indicate that we are padding up to 4 ints of preamble for 64-bit code, and then for compat mode we need to pad differently, using only 3 ints. Second, the C ABI requires a save area of two registers, not two pointers, since in compat mode we have 64-bit registers all of which we need to save, even though we only have 32-bit VAs. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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@ -59,9 +59,7 @@
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* The ABI requires callers to allocate a caller state save area of
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* this many bytes at the bottom of each stack frame.
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*/
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#ifdef __tile__
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#define C_ABI_SAVE_AREA_SIZE (2 * __SIZEOF_POINTER__)
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#endif
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#define C_ABI_SAVE_AREA_SIZE (2 * (CHIP_WORD_SIZE() / 8))
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/**
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* The operand to an 'info' opcode directing the backtracer to not
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@ -17,6 +17,10 @@
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#define __ARCH_SI_TRAPNO
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#ifdef __LP64__
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# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
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#endif
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#include <asm-generic/siginfo.h>
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/*
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@ -56,13 +56,15 @@ struct compat_ucontext {
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sigset_t uc_sigmask; /* mask last for extensibility */
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};
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#define COMPAT_SI_PAD_SIZE ((SI_MAX_SIZE - 3 * sizeof(int)) / sizeof(int))
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struct compat_siginfo {
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int si_signo;
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int si_errno;
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int si_code;
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union {
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int _pad[SI_PAD_SIZE];
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int _pad[COMPAT_SI_PAD_SIZE];
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/* kill() */
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struct {
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