arch/tile: Fix a couple of issues with the COMPAT code for TILE-Gx.

First, the siginfo preamble wasn't quite right; we need to indicate
that we are padding up to 4 ints of preamble for 64-bit code, and
then for compat mode we need to pad differently, using only 3 ints.

Second, the C ABI requires a save area of two registers, not two
pointers, since in compat mode we have 64-bit registers all of which
we need to save, even though we only have 32-bit VAs.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf 2010-08-13 08:32:21 -04:00
parent 749dc6f252
commit 32020effaf
3 changed files with 8 additions and 4 deletions

View File

@ -59,9 +59,7 @@
* The ABI requires callers to allocate a caller state save area of
* this many bytes at the bottom of each stack frame.
*/
#ifdef __tile__
#define C_ABI_SAVE_AREA_SIZE (2 * __SIZEOF_POINTER__)
#endif
#define C_ABI_SAVE_AREA_SIZE (2 * (CHIP_WORD_SIZE() / 8))
/**
* The operand to an 'info' opcode directing the backtracer to not

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@ -17,6 +17,10 @@
#define __ARCH_SI_TRAPNO
#ifdef __LP64__
# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
#endif
#include <asm-generic/siginfo.h>
/*

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@ -56,13 +56,15 @@ struct compat_ucontext {
sigset_t uc_sigmask; /* mask last for extensibility */
};
#define COMPAT_SI_PAD_SIZE ((SI_MAX_SIZE - 3 * sizeof(int)) / sizeof(int))
struct compat_siginfo {
int si_signo;
int si_errno;
int si_code;
union {
int _pad[SI_PAD_SIZE];
int _pad[COMPAT_SI_PAD_SIZE];
/* kill() */
struct {