forked from luck/tmp_suning_uos_patched
ASoC: cs35l33: Initial commit of the cs35l33 CODEC driver.
Initial commit of the Cirrus Logic cs35l33 8V boosted class D amplifier. Signed-off-by: Paul Handrigan <Paul.Handrigan@cirrus.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Paul Handrigan
Mark Brown
parent
1a695a905c
commit
3333cb7187
48
include/sound/cs35l33.h
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48
include/sound/cs35l33.h
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@ -0,0 +1,48 @@
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/*
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* linux/sound/cs35l33.h -- Platform data for CS35l33
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*
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* Copyright (c) 2016 Cirrus Logic Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __CS35L33_H
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#define __CS35L33_H
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struct cs35l33_hg {
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bool enable_hg_algo;
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unsigned int mem_depth;
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unsigned int release_rate;
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unsigned int hd_rm;
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unsigned int ldo_thld;
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unsigned int ldo_path_disable;
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unsigned int ldo_entry_delay;
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bool vp_hg_auto;
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unsigned int vp_hg;
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unsigned int vp_hg_rate;
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unsigned int vp_hg_va;
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};
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struct cs35l33_pdata {
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/* Boost Controller Voltage Setting */
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unsigned int boost_ctl;
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/* Boost Controller Peak Current */
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unsigned int boost_ipk;
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/* Amplifier Drive Select */
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unsigned int amp_drv_sel;
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/* soft volume ramp */
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unsigned int ramp_rate;
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/* IMON adc scale */
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unsigned int imon_adc_scale;
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/* H/G algo configuration */
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struct cs35l33_hg hg_config;
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};
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#endif /* __CS35L33_H */
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@ -46,6 +46,7 @@ config SND_SOC_ALL_CODECS
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select SND_SOC_BT_SCO
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select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC
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select SND_SOC_CS35L32 if I2C
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select SND_SOC_CS35L33 if I2C
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select SND_SOC_CS42L51_I2C if I2C
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select SND_SOC_CS42L52 if I2C && INPUT
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select SND_SOC_CS42L56 if I2C && INPUT
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@ -380,6 +381,10 @@ config SND_SOC_CS35L32
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tristate "Cirrus Logic CS35L32 CODEC"
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depends on I2C
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config SND_SOC_CS35L33
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tristate "Cirrus Logic CS35L33 CODEC"
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depends on I2C
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config SND_SOC_CS42L51
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tristate
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@ -35,6 +35,7 @@ snd-soc-arizona-objs := arizona.o
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snd-soc-bt-sco-objs := bt-sco.o
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snd-soc-cq93vc-objs := cq93vc.o
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snd-soc-cs35l32-objs := cs35l32.o
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snd-soc-cs35l33-objs := cs35l33.o
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snd-soc-cs42l51-objs := cs42l51.o
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snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o
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snd-soc-cs42l52-objs := cs42l52.o
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@ -250,6 +251,7 @@ obj-$(CONFIG_SND_SOC_ARIZONA) += snd-soc-arizona.o
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obj-$(CONFIG_SND_SOC_BT_SCO) += snd-soc-bt-sco.o
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obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o
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obj-$(CONFIG_SND_SOC_CS35L32) += snd-soc-cs35l32.o
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obj-$(CONFIG_SND_SOC_CS35L33) += snd-soc-cs35l33.o
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obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o
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obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o
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obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o
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1315
sound/soc/codecs/cs35l33.c
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1315
sound/soc/codecs/cs35l33.c
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File diff suppressed because it is too large
Load Diff
221
sound/soc/codecs/cs35l33.h
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221
sound/soc/codecs/cs35l33.h
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@ -0,0 +1,221 @@
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/*
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* cs35l33.h -- CS35L33 ALSA SoC audio driver
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*
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* Copyright 2016 Cirrus Logic, Inc.
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*
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* Author: Paul Handrigan <paul.handrigan@cirrus.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __CS35L33_H__
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#define __CS35L33_H__
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#define CS35L33_CHIP_ID 0x00035A33
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#define CS35L33_DEVID_AB 0x01 /* Device ID A & B [RO] */
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#define CS35L33_DEVID_CD 0x02 /* Device ID C & D [RO] */
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#define CS35L33_DEVID_E 0x03 /* Device ID E [RO] */
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#define CS35L33_FAB_ID 0x04 /* Fab ID [RO] */
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#define CS35L33_REV_ID 0x05 /* Revision ID [RO] */
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#define CS35L33_PWRCTL1 0x06 /* Power Ctl 1 */
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#define CS35L33_PWRCTL2 0x07 /* Power Ctl 2 */
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#define CS35L33_CLK_CTL 0x08 /* Clock Ctl */
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#define CS35L33_BST_PEAK_CTL 0x09 /* Max Current for Boost */
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#define CS35L33_PROTECT_CTL 0x0A /* Amp Protection Parameters */
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#define CS35L33_BST_CTL1 0x0B /* Boost Converter CTL1 */
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#define CS35L33_BST_CTL2 0x0C /* Boost Converter CTL2 */
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#define CS35L33_ADSP_CTL 0x0D /* Serial Port Control */
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#define CS35L33_ADC_CTL 0x0E /* ADC Control */
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#define CS35L33_DAC_CTL 0x0F /* DAC Control */
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#define CS35L33_DIG_VOL_CTL 0x10 /* Digital Volume CTL */
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#define CS35L33_CLASSD_CTL 0x11 /* Class D Amp CTL */
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#define CS35L33_AMP_CTL 0x12 /* Amp Gain/Protecton Release CTL */
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#define CS35L33_INT_MASK_1 0x13 /* Interrupt Mask 1 */
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#define CS35L33_INT_MASK_2 0x14 /* Interrupt Mask 2 */
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#define CS35L33_INT_STATUS_1 0x15 /* Interrupt Status 1 [RO] */
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#define CS35L33_INT_STATUS_2 0x16 /* Interrupt Status 2 [RO] */
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#define CS35L33_DIAG_LOCK 0x17 /* Diagnostic Mode Register Lock */
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#define CS35L33_DIAG_CTRL_1 0x18 /* Diagnostic Mode Register Control */
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#define CS35L33_DIAG_CTRL_2 0x19 /* Diagnostic Mode Register Control 2 */
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#define CS35L33_HG_MEMLDO_CTL 0x23 /* H/G Memory/LDO CTL */
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#define CS35L33_HG_REL_RATE 0x24 /* H/G Release Rate */
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#define CS35L33_LDO_DEL 0x25 /* LDO Entry Delay/VPhg Control 1 */
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#define CS35L33_HG_HEAD 0x29 /* H/G Headroom */
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#define CS35L33_HG_EN 0x2A /* H/G Enable/VPhg CNT2 */
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#define CS35L33_TX_VMON 0x2D /* TDM TX Control 1 (VMON) */
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#define CS35L33_TX_IMON 0x2E /* TDM TX Control 2 (IMON) */
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#define CS35L33_TX_VPMON 0x2F /* TDM TX Control 3 (VPMON) */
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#define CS35L33_TX_VBSTMON 0x30 /* TDM TX Control 4 (VBSTMON) */
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#define CS35L33_TX_FLAG 0x31 /* TDM TX Control 5 (FLAG) */
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#define CS35L33_TX_EN1 0x32 /* TDM TX Enable 1 */
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#define CS35L33_TX_EN2 0x33 /* TDM TX Enable 2 */
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#define CS35L33_TX_EN3 0x34 /* TDM TX Enable 3 */
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#define CS35L33_TX_EN4 0x35 /* TDM TX Enable 4 */
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#define CS35L33_RX_AUD 0x36 /* TDM RX Control 1 */
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#define CS35L33_RX_SPLY 0x37 /* TDM RX Control 2 */
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#define CS35L33_RX_ALIVE 0x38 /* TDM RX Control 3 */
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#define CS35L33_BST_CTL4 0x39 /* Boost Converter Control 4 */
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#define CS35L33_HG_STATUS 0x3F /* H/G Status */
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#define CS35L33_MAX_REGISTER 0x59
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#define CS35L33_MCLK_5644 5644800
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#define CS35L33_MCLK_6144 6144000
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#define CS35L33_MCLK_6 6000000
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#define CS35L33_MCLK_11289 11289600
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#define CS35L33_MCLK_12 12000000
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#define CS35L33_MCLK_12288 12288000
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/* CS35L33_PWRCTL1 */
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#define CS35L33_PDN_AMP (1 << 7)
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#define CS35L33_PDN_BST (1 << 2)
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#define CS35L33_PDN_ALL 1
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/* CS35L33_PWRCTL2 */
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#define CS35L33_PDN_VMON_SHIFT 7
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#define CS35L33_PDN_VMON (1 << CS35L33_PDN_VMON_SHIFT)
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#define CS35L33_PDN_IMON_SHIFT 6
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#define CS35L33_PDN_IMON (1 << CS35L33_PDN_IMON_SHIFT)
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#define CS35L33_PDN_VPMON_SHIFT 5
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#define CS35L33_PDN_VPMON (1 << CS35L33_PDN_VPMON_SHIFT)
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#define CS35L33_PDN_VBSTMON_SHIFT 4
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#define CS35L33_PDN_VBSTMON (1 << CS35L33_PDN_VBSTMON_SHIFT)
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#define CS35L33_SDOUT_3ST_I2S_SHIFT 3
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#define CS35L33_SDOUT_3ST_I2S (1 << CS35L33_SDOUT_3ST_I2S_SHIFT)
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#define CS35L33_PDN_SDIN_SHIFT 2
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#define CS35L33_PDN_SDIN (1 << CS35L33_PDN_SDIN_SHIFT)
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#define CS35L33_PDN_TDM_SHIFT 1
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#define CS35L33_PDN_TDM (1 << CS35L33_PDN_TDM_SHIFT)
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/* CS35L33_CLK_CTL */
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#define CS35L33_MCLKDIS (1 << 7)
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#define CS35L33_MCLKDIV2 (1 << 6)
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#define CS35L33_SDOUT_3ST_TDM (1 << 5)
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#define CS35L33_INT_FS_RATE (1 << 4)
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#define CS35L33_ADSP_FS 0xF
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/* CS35L33_PROTECT_CTL */
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#define CS35L33_ALIVE_WD_DIS (3 << 2)
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/* CS35L33_BST_CTL1 */
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#define CS35L33_BST_CTL_SRC (1 << 6)
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#define CS35L33_BST_CTL_SHIFT (1 << 5)
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#define CS35L33_BST_CTL_MASK 0x3F
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/* CS35L33_BST_CTL2 */
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#define CS35L33_TDM_WD_SEL (1 << 4)
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#define CS35L33_ALIVE_WD_DIS2 (1 << 3)
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#define CS35L33_VBST_SR_STEP 0x3
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/* CS35L33_ADSP_CTL */
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#define CS35L33_ADSP_DRIVE (1 << 7)
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#define CS35L33_MS_MASK (1 << 6)
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#define CS35L33_SDIN_LOC (3 << 4)
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#define CS35L33_ALIVE_RATE 0x3
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/* CS35L33_ADC_CTL */
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#define CS35L33_INV_VMON (1 << 7)
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#define CS35L33_INV_IMON (1 << 6)
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#define CS35L33_ADC_NOTCH_DIS (1 << 5)
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#define CS35L33_IMON_SCALE 0xF
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/* CS35L33_DAC_CTL */
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#define CS35L33_INV_DAC (1 << 7)
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#define CS35L33_DAC_NOTCH_DIS (1 << 5)
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#define CS35L33_DIGSFT (1 << 4)
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#define CS35L33_DSR_RATE 0xF
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/* CS35L33_CLASSD_CTL */
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#define CS35L33_AMP_SD (1 << 6)
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#define CS35L33_AMP_DRV_SEL_SRC (1 << 5)
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#define CS35L33_AMP_DRV_SEL_MASK 0x10
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#define CS35L33_AMP_DRV_SEL_SHIFT 4
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#define CS35L33_AMP_CAL (1 << 3)
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#define CS35L33_GAIN_CHG_ZC_MASK 0x04
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#define CS35L33_GAIN_CHG_ZC_SHIFT 2
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#define CS35L33_CLASS_D_CTL_MASK 0x3F
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/* CS35L33_AMP_CTL */
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#define CS35L33_AMP_GAIN 0xF0
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#define CS35L33_CAL_ERR_RLS (1 << 3)
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#define CS35L33_AMP_SHORT_RLS (1 << 2)
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#define CS35L33_OTW_RLS (1 << 1)
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#define CS35L33_OTE_RLS 1
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/* CS35L33_INT_MASK_1 */
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#define CS35L33_M_CAL_ERR_SHIFT 6
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#define CS35L33_M_CAL_ERR (1 << CS35L33_M_CAL_ERR_SHIFT)
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#define CS35L33_M_ALIVE_ERR_SHIFT 5
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#define CS35L33_M_ALIVE_ERR (1 << CS35L33_M_ALIVE_ERR_SHIFT)
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#define CS35L33_M_AMP_SHORT_SHIFT 2
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#define CS35L33_M_AMP_SHORT (1 << CS35L33_M_AMP_SHORT_SHIFT)
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#define CS35L33_M_OTW_SHIFT 1
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#define CS35L33_M_OTW (1 << CS35L33_M_OTW_SHIFT)
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#define CS35L33_M_OTE_SHIFT 0
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#define CS35L33_M_OTE (1 << CS35L33_M_OTE_SHIFT)
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/* CS35L33_INT_STATUS_1 */
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#define CS35L33_CAL_ERR (1 << 6)
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#define CS35L33_ALIVE_ERR (1 << 5)
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#define CS35L33_ADSPCLK_ERR (1 << 4)
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#define CS35L33_MCLK_ERR (1 << 3)
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#define CS35L33_AMP_SHORT (1 << 2)
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#define CS35L33_OTW (1 << 1)
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#define CS35L33_OTE (1 << 0)
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/* CS35L33_INT_STATUS_2 */
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#define CS35L33_VMON_OVFL (1 << 7)
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#define CS35L33_IMON_OVFL (1 << 6)
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#define CS35L33_VPMON_OVFL (1 << 5)
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#define CS35L33_VBSTMON_OVFL (1 << 4)
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#define CS35L33_PDN_DONE 1
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/* CS35L33_BST_CTL4 */
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#define CS35L33_BST_RGS 0x70
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#define CS35L33_BST_COEFF3 0xF
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/* CS35L33_HG_MEMLDO_CTL */
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#define CS35L33_MEM_DEPTH_SHIFT 5
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#define CS35L33_MEM_DEPTH_MASK (0x3 << CS35L33_MEM_DEPTH_SHIFT)
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#define CS35L33_LDO_THLD_SHIFT 1
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#define CS35L33_LDO_THLD_MASK (0xF << CS35L33_LDO_THLD_SHIFT)
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#define CS35L33_LDO_DISABLE_SHIFT 0
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#define CS35L33_LDO_DISABLE_MASK (0x1 << CS35L33_LDO_DISABLE_SHIFT)
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/* CS35L33_LDO_DEL */
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#define CS35L33_VP_HG_VA_SHIFT 5
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#define CS35L33_VP_HG_VA_MASK (0x7 << CS35L33_VP_HG_VA_SHIFT)
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#define CS35L33_LDO_ENTRY_DELAY_SHIFT 2
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#define CS35L33_LDO_ENTRY_DELAY_MASK (0x7 << CS35L33_LDO_ENTRY_DELAY_SHIFT)
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#define CS35L33_VP_HG_RATE_SHIFT 0
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#define CS35L33_VP_HG_RATE_MASK (0x3 << CS35L33_VP_HG_RATE_SHIFT)
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/* CS35L33_HG_HEAD */
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#define CS35L33_HD_RM_SHIFT 0
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#define CS35L33_HD_RM_MASK (0x7F << CS35L33_HD_RM_SHIFT)
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/* CS35L33_HG_EN */
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#define CS35L33_CLASS_HG_ENA_SHIFT 7
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#define CS35L33_CLASS_HG_EN_MASK (0x1 << CS35L33_CLASS_HG_ENA_SHIFT)
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#define CS35L33_VP_HG_AUTO_SHIFT 6
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#define CS35L33_VP_HG_AUTO_MASK (0x1 << 6)
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#define CS35L33_VP_HG_SHIFT 0
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#define CS35L33_VP_HG_MASK (0x1F << CS35L33_VP_HG_SHIFT)
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#define CS35L33_RATES (SNDRV_PCM_RATE_8000_48000)
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#define CS35L33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S24_LE)
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/* CS35L33_{RX,TX}_X */
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#define CS35L33_X_STATE_SHIFT 7
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#define CS35L33_X_STATE (1 << CS35L33_X_STATE_SHIFT)
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#define CS35L33_X_LOC_SHIFT 0
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#define CS35L33_X_LOC (0x1F << CS35L33_X_LOC_SHIFT)
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/* CS35L33_RX_AUD */
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#define CS35L33_AUDIN_RX_DEPTH_SHIFT 5
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#define CS35L33_AUDIN_RX_DEPTH (0x7 << CS35L33_AUDIN_RX_DEPTH_SHIFT)
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#endif
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