forked from luck/tmp_suning_uos_patched
clk: gxbb: add MMC gate clocks, and expose for DT
Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -583,6 +583,9 @@ static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);
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static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);
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static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
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static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
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static MESON_GATE(emmc_a, HHI_GCLK_MPEG0, 24);
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static MESON_GATE(emmc_b, HHI_GCLK_MPEG0, 25);
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static MESON_GATE(emmc_c, HHI_GCLK_MPEG0, 26);
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static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);
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static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
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@ -748,6 +751,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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[CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
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[CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
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[CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
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[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
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[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
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[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
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},
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.num = NR_CLKS,
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};
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@ -847,6 +853,9 @@ static struct clk_gate *gxbb_clk_gates[] = {
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&gxbb_ao_ahb_bus,
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&gxbb_ao_iface,
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&gxbb_ao_i2c,
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&gxbb_emmc_a,
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&gxbb_emmc_b,
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&gxbb_emmc_c,
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};
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static int gxbb_clkc_probe(struct platform_device *pdev)
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@ -172,7 +172,7 @@
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/* CLKID_CPUCLK */
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#define CLKID_HDMI_PLL 2
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#define CLKID_FIXED_PLL 3
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#define CLKID_FCLK_DIV2 4
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/* CLKID_FCLK_DIV2 */
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#define CLKID_FCLK_DIV3 5
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#define CLKID_FCLK_DIV4 6
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#define CLKID_FCLK_DIV5 7
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@ -262,8 +262,11 @@
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#define CLKID_AO_AHB_BUS 91
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#define CLKID_AO_IFACE 92
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#define CLKID_AO_I2C 93
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/* CLKID_SD_EMMC_A */
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/* CLKID_SD_EMMC_B */
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/* CLKID_SD_EMMC_C */
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#define NR_CLKS 94
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#define NR_CLKS 97
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/* include the CLKIDs that have been made part of the stable DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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@ -6,7 +6,11 @@
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#define __GXBB_CLKC_H
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#define CLKID_CPUCLK 1
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#define CLKID_FCLK_DIV2 4
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#define CLKID_CLK81 12
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#define CLKID_ETH 36
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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#define CLKID_SD_EMMC_C 96
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#endif /* __GXBB_CLKC_H */
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