forked from luck/tmp_suning_uos_patched
clocksource: sh_cmt: __clocksource_updatefreq_hz() update
This patch updates the clocksource part of the CMT driver to make use of the __clocksource_updatefreq_hz() function. Without this patch the old code uses clocksource_register() together with a hack that assumes a never changing clock rate (see clk_enable(), clk_get_rate() and clk_disable()). The patch uses clocksource_register_hz() with 1 Hz as initial value, then lets the ->enable() callback update the value with __clocksource_updatefreq_hz() once the struct clk has been enabled and the frequency is stable. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: John Stultz <johnstul@us.ibm.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -416,11 +416,15 @@ static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
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static int sh_cmt_clocksource_enable(struct clocksource *cs)
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{
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int ret;
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struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
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p->total_cycles = 0;
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return sh_cmt_start(p, FLAG_CLOCKSOURCE);
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ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
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if (!ret)
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__clocksource_updatefreq_hz(cs, p->rate);
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return ret;
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}
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static void sh_cmt_clocksource_disable(struct clocksource *cs)
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@ -448,19 +452,10 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
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cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
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cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
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/* clk_get_rate() needs an enabled clock */
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clk_enable(p->clk);
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p->rate = clk_get_rate(p->clk) / ((p->width == 16) ? 512 : 8);
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clk_disable(p->clk);
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/* TODO: calculate good shift from rate and counter bit width */
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cs->shift = 0;
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cs->mult = clocksource_hz2mult(p->rate, cs->shift);
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dev_info(&p->pdev->dev, "used as clock source\n");
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clocksource_register(cs);
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/* Register with dummy 1 Hz value, gets updated in ->enable() */
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clocksource_register_hz(cs, 1);
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return 0;
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}
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