forked from luck/tmp_suning_uos_patched
[ARM] 5031/1: Indentation correction in cpu-pxa.c.
These indentation corrections prepare the pxa27x support. Signed-off-by: Robert Jarzmik <rjarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Robert Jarzmik
Russell King
parent
ebdf982aae
commit
3679389b88
@ -57,29 +57,29 @@ typedef struct {
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} pxa_freqs_t;
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
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#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
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#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
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#define CCLKCFG_TURBO 0x1
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#define CCLKCFG_FCS 0x2
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#define PXA25x_MIN_FREQ 99500
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#define PXA25x_MAX_FREQ 398100
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
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#define MDREFR_DRI_MASK 0xFFF
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#define CCLKCFG_TURBO 0x1
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#define CCLKCFG_FCS 0x2
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#define PXA25x_MIN_FREQ 99500
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#define PXA25x_MAX_FREQ 398100
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
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#define MDREFR_DRI_MASK 0xFFF
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/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
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static pxa_freqs_t pxa255_run_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2*/
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{ 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */
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{132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */
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{199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */
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{265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
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{331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
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{398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */
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{0,}
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/* CPU MEMBUS CCCR DIV2 run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1}, /* 99, 99, 50, 50 */
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{132700, 132700, 0x123, 1}, /* 133, 133, 66, 66 */
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{199100, 99500, 0x141, 0}, /* 199, 199, 99, 99 */
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{265400, 132700, 0x143, 1}, /* 265, 265, 133, 66 */
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{331800, 165900, 0x145, 1}, /* 331, 331, 166, 83 */
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{398100, 99500, 0x161, 0}, /* 398, 398, 196, 99 */
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{0,}
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};
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#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
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@ -88,17 +88,18 @@ static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
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/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
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static pxa_freqs_t pxa255_turbo_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2*/
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{ 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */
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{199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */
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{298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */
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{298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
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{398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */
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{0,}
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/* CPU MEMBUS CCCR DIV2 run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1}, /* 99, 99, 50, 50 */
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{199100, 99500, 0x221, 0}, /* 99, 199, 50, 99 */
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{298500, 99500, 0x321, 0}, /* 99, 287, 50, 99 */
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{298600, 99500, 0x1c1, 0}, /* 199, 287, 99, 99 */
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{398100, 99500, 0x241, 0}, /* 199, 398, 99, 99 */
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{0,}
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};
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#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
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static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
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static struct cpufreq_frequency_table
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pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
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extern unsigned get_clk_frequency_khz(int info);
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@ -122,14 +123,14 @@ static int pxa_verify_policy(struct cpufreq_policy *policy)
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if (freq_debug)
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pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
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policy->min, policy->max);
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policy->min, policy->max);
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return ret;
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}
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static int pxa_set_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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unsigned int target_freq,
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unsigned int relation)
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{
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struct cpufreq_frequency_table *pxa_freqs_table;
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pxa_freqs_t *pxa_freq_settings;
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@ -155,7 +156,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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/* Lookup the next frequency */
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if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
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target_freq, relation, &idx)) {
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target_freq, relation, &idx)) {
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return -EINVAL;
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}
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@ -164,10 +165,11 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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freqs.cpu = policy->cpu;
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if (freq_debug)
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pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
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freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
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(pxa_freq_settings[idx].membus / 2000) :
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(pxa_freq_settings[idx].membus / 1000));
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pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
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"(SDRAM %d Mhz)\n",
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freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
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(pxa_freq_settings[idx].membus / 2000) :
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(pxa_freq_settings[idx].membus / 1000));
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/*
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* Tell everyone what we're about to do...
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@ -177,16 +179,17 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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/* Calculate the next MDREFR. If we're slowing down the SDRAM clock
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* we need to preset the smaller DRI before the change. If we're speeding
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* up we need to set the larger DRI value after the change.
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* we need to preset the smaller DRI before the change. If we're
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* speeding up we need to set the larger DRI value after the change.
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*/
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preset_mdrefr = postset_mdrefr = MDREFR;
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if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
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if ((MDREFR & MDREFR_DRI_MASK) >
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MDREFR_DRI(pxa_freq_settings[idx].membus)) {
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preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
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MDREFR_DRI(pxa_freq_settings[idx].membus);
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MDREFR_DRI(pxa_freq_settings[idx].membus);
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}
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postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
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MDREFR_DRI(pxa_freq_settings[idx].membus);
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MDREFR_DRI(pxa_freq_settings[idx].membus);
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/* If we're dividing the memory clock by two for the SDRAM clock, this
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* must be set prior to the change. Clearing the divide must be done
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@ -207,7 +210,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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asm volatile(" \n\
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ldr r4, [%1] /* load MDREFR */ \n\
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b 2f \n\
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.align 5 \n\
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.align 5 \n\
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1: \n\
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str %4, [%1] /* preset the MDREFR */ \n\
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mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
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@ -217,10 +220,10 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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2: b 1b \n\
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3: nop \n\
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"
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: "=&r" (unused)
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: "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
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"r" (preset_mdrefr), "r" (postset_mdrefr)
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: "r4", "r5");
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: "=&r" (unused)
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: "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
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"r" (preset_mdrefr), "r" (postset_mdrefr)
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: "r4", "r5");
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local_irq_restore(flags);
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/*
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@ -248,7 +251,7 @@ static int pxa_cpufreq_init(struct cpufreq_policy *policy)
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policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
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policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
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policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
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policy->cur = get_clk_frequency_khz(0); /* current freq */
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policy->cur = get_clk_frequency_khz(0); /* current freq */
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policy->min = policy->max = policy->cur;
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/* Generate the run cpufreq_frequency_table struct */
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@ -260,7 +263,8 @@ static int pxa_cpufreq_init(struct cpufreq_policy *policy)
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pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
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/* Generate the turbo cpufreq_frequency_table struct */
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for (i = 0; i < NUM_TURBO_FREQS; i++) {
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pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz;
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pxa255_turbo_freq_table[i].frequency =
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pxa255_turbo_freqs[i].khz;
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pxa255_turbo_freq_table[i].index = i;
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}
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pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
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@ -293,8 +297,8 @@ static void __exit pxa_cpu_exit(void)
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}
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MODULE_AUTHOR ("Intrinsyc Software Inc.");
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MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
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MODULE_AUTHOR("Intrinsyc Software Inc.");
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MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
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MODULE_LICENSE("GPL");
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module_init(pxa_cpu_init);
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module_exit(pxa_cpu_exit);
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