forked from luck/tmp_suning_uos_patched
KVM: arm/arm64: vgic-its: Free caches when GITS_BASER Valid bit is cleared
When the GITS_BASER<n>.Valid gets cleared, the data structures in guest RAM are not valid anymore. The device, collection and LPI lists stored in the in-kernel ITS represent the same information in some form of cache. So let's void the cache. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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@ -1431,7 +1431,7 @@ static void vgic_mmio_write_its_baser(struct kvm *kvm,
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unsigned long val)
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{
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const struct vgic_its_abi *abi = vgic_its_get_abi(its);
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u64 entry_size, device_type;
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u64 entry_size, table_type;
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u64 reg, *regptr, clearbits = 0;
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/* When GITS_CTLR.Enable is 1, we ignore write accesses. */
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@ -1442,12 +1442,12 @@ static void vgic_mmio_write_its_baser(struct kvm *kvm,
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case 0:
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regptr = &its->baser_device_table;
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entry_size = abi->dte_esz;
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device_type = GITS_BASER_TYPE_DEVICE;
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table_type = GITS_BASER_TYPE_DEVICE;
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break;
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case 1:
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regptr = &its->baser_coll_table;
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entry_size = abi->cte_esz;
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device_type = GITS_BASER_TYPE_COLLECTION;
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table_type = GITS_BASER_TYPE_COLLECTION;
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clearbits = GITS_BASER_INDIRECT;
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break;
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default:
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@ -1459,10 +1459,24 @@ static void vgic_mmio_write_its_baser(struct kvm *kvm,
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reg &= ~clearbits;
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reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
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reg |= device_type << GITS_BASER_TYPE_SHIFT;
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reg |= table_type << GITS_BASER_TYPE_SHIFT;
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reg = vgic_sanitise_its_baser(reg);
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*regptr = reg;
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if (!(reg & GITS_BASER_VALID)) {
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/* Take the its_lock to prevent a race with a save/restore */
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mutex_lock(&its->its_lock);
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switch (table_type) {
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case GITS_BASER_TYPE_DEVICE:
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vgic_its_free_device_list(kvm, its);
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break;
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case GITS_BASER_TYPE_COLLECTION:
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vgic_its_free_collection_list(kvm, its);
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break;
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}
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mutex_unlock(&its->its_lock);
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}
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}
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static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
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