forked from luck/tmp_suning_uos_patched
mtd: nand: xway: add nandaddr to own struct
Instead of using IO_ADDR_W and IO_ADDR_R use an own pointer to the NAND controller memory area. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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250d45eb82
commit
37987ba4d1
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@ -66,22 +66,23 @@
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struct xway_nand_data {
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struct nand_chip chip;
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unsigned long csflags;
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void __iomem *nandaddr;
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};
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static u8 xway_readb(struct mtd_info *mtd, int op)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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void __iomem *nandaddr = chip->IO_ADDR_R;
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struct xway_nand_data *data = nand_get_controller_data(chip);
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return readb(nandaddr + op);
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return readb(data->nandaddr + op);
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}
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static void xway_writeb(struct mtd_info *mtd, int op, u8 value)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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void __iomem *nandaddr = chip->IO_ADDR_W;
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struct xway_nand_data *data = nand_get_controller_data(chip);
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writeb(value, nandaddr + op);
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writeb(value, data->nandaddr + op);
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}
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static void xway_select_chip(struct mtd_info *mtd, int select)
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@ -154,7 +155,6 @@ static int xway_nand_probe(struct platform_device *pdev)
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struct mtd_info *mtd;
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struct resource *res;
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int err;
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void __iomem *nandaddr;
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u32 cs;
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u32 cs_flag = 0;
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@ -165,16 +165,14 @@ static int xway_nand_probe(struct platform_device *pdev)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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nandaddr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(nandaddr))
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return PTR_ERR(nandaddr);
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data->nandaddr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->nandaddr))
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return PTR_ERR(data->nandaddr);
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nand_set_flash_node(&data->chip, pdev->dev.of_node);
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mtd = nand_to_mtd(&data->chip);
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mtd->dev.parent = &pdev->dev;
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data->chip.IO_ADDR_R = nandaddr;
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data->chip.IO_ADDR_W = nandaddr;
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data->chip.cmd_ctrl = xway_cmd_ctrl;
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data->chip.dev_ready = xway_dev_ready;
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data->chip.select_chip = xway_select_chip;
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@ -195,16 +193,16 @@ static int xway_nand_probe(struct platform_device *pdev)
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cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
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/* setup the EBU to run in NAND mode on our base addr */
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ltq_ebu_w32(CPHYSADDR(nandaddr)
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| ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
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ltq_ebu_w32(CPHYSADDR(data->nandaddr)
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| ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
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ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
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| BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
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| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
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| BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
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| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
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ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
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| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
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| cs_flag, EBU_NAND_CON);
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| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
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| cs_flag, EBU_NAND_CON);
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/* Scan to find existence of the device */
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err = nand_scan(mtd, 1);
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