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[media] rc/nuvoton-cir: enable CIR on w83667hg chip variant

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Thanks to some excellent investigative work by Douglas Clowes, it was
uncovered that the older w83667hg Nuvoton chip functions with this
driver after actually enabling the CIR function via its multi-function
chip config register. The CIR and CIR wide-band sensor enable bits are
just in a different place on this hardware, so we only poke register
0x27 on 677 hardware now, and we poke register 0x2c on the 667 now.

Reported-by: Douglas Clowes <dclowes1@optusnet.com.au>
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Jarod Wilson 2011-04-12 13:38:27 -03:00 committed by Mauro Carvalho Chehab
parent 362d3a3a95
commit 39381d4fcd
2 changed files with 23 additions and 6 deletions
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22
drivers/media/rc/nuvoton-cir.c
View File

@ -291,13 +291,23 @@ static int nvt_hw_detect(struct nvt_dev *nvt)
static void nvt_cir_ldev_init(struct nvt_dev *nvt)
{
u8 val;
u8 val, psreg, psmask, psval;
/* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
val &= OUTPUT_PIN_SEL_MASK;
val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
if (nvt->chip_major == CHIP_ID_HIGH_667) {
psreg = CR_MULTIFUNC_PIN_SEL;
psmask = MULTIFUNC_PIN_SEL_MASK;
psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
} else {
psreg = CR_OUTPUT_PIN_SEL;
psmask = OUTPUT_PIN_SEL_MASK;
psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
}
/* output pin selection: enable CIR, with WB sensor enabled */
val = nvt_cr_read(nvt, psreg);
val &= psmask;
val |= psval;
nvt_cr_write(nvt, val, psreg);
/* Select CIR logical device and enable */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);

7
drivers/media/rc/nuvoton-cir.h
View File

@ -345,6 +345,7 @@ struct nvt_dev {
#define CR_CHIP_ID_LO 0x21
#define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */
#define CR_OUTPUT_PIN_SEL 0x27
#define CR_MULTIFUNC_PIN_SEL 0x2c
#define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */
/* next three regs valid for both the CIR and CIR_WAKE logical devices */
#define CR_CIR_BASE_ADDR_HI 0x60
@ -368,10 +369,16 @@ struct nvt_dev {
#define CIR_INTR_MOUSE_IRQ_BIT 0x80
#define PME_INTR_CIR_PASS_BIT 0x08
/* w83677hg CIR pin config */
#define OUTPUT_PIN_SEL_MASK 0xbc
#define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
#define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */
/* w83667hg CIR pin config */
#define MULTIFUNC_PIN_SEL_MASK 0x1f
#define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
#define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */
/* MCE CIR signal length, related on sample period */
/* MCE CIR controller signal length: about 43ms