forked from luck/tmp_suning_uos_patched
ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling code
This code is becoming duplicated in many places. So let's consolidate it into a handy macro that is known to be right and available for reuse. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Nicolas Pitre
Russell King
parent
3c8828f6a0
commit
39792c7cf3
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@ -435,4 +435,50 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
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#define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr))
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#define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr))
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/*
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* Disabling cache access for one CPU in an ARMv7 SMP system is tricky.
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* To do so we must:
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*
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* - Clear the SCTLR.C bit to prevent further cache allocations
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* - Flush the desired level of cache
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* - Clear the ACTLR "SMP" bit to disable local coherency
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*
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* ... and so without any intervening memory access in between those steps,
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* not even to the stack.
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*
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* WARNING -- After this has been called:
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*
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* - No ldrex/strex (and similar) instructions must be used.
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* - The CPU is obviously no longer coherent with the other CPUs.
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* - This is unlikely to work as expected if Linux is running non-secure.
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*
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* Note:
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*
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* - This is known to apply to several ARMv7 processor implementations,
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* however some exceptions may exist. Caveat emptor.
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*
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* - The clobber list is dictated by the call to v7_flush_dcache_*.
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* fp is preserved to the stack explicitly prior disabling the cache
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* since adding it to the clobber list is incompatible with having
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* CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering
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* trampoline are inserted by the linker and to keep sp 64-bit aligned.
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*/
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#define v7_exit_coherency_flush(level) \
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asm volatile( \
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"stmfd sp!, {fp, ip} \n\t" \
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"mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
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"bic r0, r0, #"__stringify(CR_C)" \n\t" \
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"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
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"isb \n\t" \
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"bl v7_flush_dcache_"__stringify(level)" \n\t" \
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"clrex \n\t" \
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"mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
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"bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
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"mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
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"isb \n\t" \
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"dsb \n\t" \
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"ldmfd sp!, {fp, ip}" \
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: : : "r0","r1","r2","r3","r4","r5","r6","r7", \
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"r9","r10","lr","memory" )
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#endif
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@ -133,38 +133,8 @@ static void dcscb_power_down(void)
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if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
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arch_spin_unlock(&dcscb_lock);
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/*
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* Flush all cache levels for this cluster.
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*
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* To do so we do:
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* - Clear the SCTLR.C bit to prevent further cache allocations
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* - Flush the whole cache
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* - Clear the ACTLR "SMP" bit to disable local coherency
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*
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* Let's do it in the safest possible way i.e. with
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* no memory access within the following sequence
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* including to the stack.
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*
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* Note: fp is preserved to the stack explicitly prior doing
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* this since adding it to the clobber list is incompatible
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* with having CONFIG_FRAME_POINTER=y.
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*/
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asm volatile(
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"str fp, [sp, #-4]! \n\t"
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"mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
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"bic r0, r0, #"__stringify(CR_C)" \n\t"
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"mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
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"isb \n\t"
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"bl v7_flush_dcache_all \n\t"
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"clrex \n\t"
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"mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
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"bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
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"mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
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"isb \n\t"
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"dsb \n\t"
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"ldr fp, [sp], #4"
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: : : "r0","r1","r2","r3","r4","r5","r6","r7",
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"r9","r10","lr","memory");
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/* Flush all cache levels for this cluster. */
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v7_exit_coherency_flush(all);
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/*
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* This is a harmless no-op. On platforms with a real
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@ -183,26 +153,8 @@ static void dcscb_power_down(void)
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} else {
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arch_spin_unlock(&dcscb_lock);
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/*
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* Flush the local CPU cache.
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* Let's do it in the safest possible way as above.
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*/
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asm volatile(
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"str fp, [sp, #-4]! \n\t"
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"mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
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"bic r0, r0, #"__stringify(CR_C)" \n\t"
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"mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
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"isb \n\t"
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"bl v7_flush_dcache_louis \n\t"
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"clrex \n\t"
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"mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
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"bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
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"mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
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"isb \n\t"
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"dsb \n\t"
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"ldr fp, [sp], #4"
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: : : "r0","r1","r2","r3","r4","r5","r6","r7",
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"r9","r10","lr","memory");
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/* Disable and flush the local CPU cache. */
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v7_exit_coherency_flush(louis);
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}
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__mcpm_cpu_down(cpu, cluster);
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@ -156,32 +156,7 @@ static void tc2_pm_down(u64 residency)
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: : "r" (0x400) );
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}
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/*
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* We need to disable and flush the whole (L1 and L2) cache.
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* Let's do it in the safest possible way i.e. with
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* no memory access within the following sequence
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* including the stack.
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*
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* Note: fp is preserved to the stack explicitly prior doing
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* this since adding it to the clobber list is incompatible
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* with having CONFIG_FRAME_POINTER=y.
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*/
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asm volatile(
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"str fp, [sp, #-4]! \n\t"
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"mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
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"bic r0, r0, #"__stringify(CR_C)" \n\t"
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"mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
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"isb \n\t"
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"bl v7_flush_dcache_all \n\t"
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"clrex \n\t"
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"mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
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"bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
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"mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
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"isb \n\t"
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"dsb \n\t"
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"ldr fp, [sp], #4"
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: : : "r0","r1","r2","r3","r4","r5","r6","r7",
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"r9","r10","lr","memory");
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v7_exit_coherency_flush(all);
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cci_disable_port_by_cpu(mpidr);
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@ -197,26 +172,7 @@ static void tc2_pm_down(u64 residency)
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arch_spin_unlock(&tc2_pm_lock);
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/*
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* We need to disable and flush only the L1 cache.
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* Let's do it in the safest possible way as above.
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*/
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asm volatile(
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"str fp, [sp, #-4]! \n\t"
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"mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
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"bic r0, r0, #"__stringify(CR_C)" \n\t"
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"mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
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"isb \n\t"
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"bl v7_flush_dcache_louis \n\t"
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"clrex \n\t"
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"mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
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"bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
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"mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
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"isb \n\t"
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"dsb \n\t"
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"ldr fp, [sp], #4"
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: : : "r0","r1","r2","r3","r4","r5","r6","r7",
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"r9","r10","lr","memory");
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v7_exit_coherency_flush(louis);
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}
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__mcpm_cpu_down(cpu, cluster);
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