forked from luck/tmp_suning_uos_patched
fjes: ES information acquisition routine
This patch adds ES information acquisition routine. ES information can be retrieved issuing information request command. ES information includes which receiver is same zone. Signed-off-by: Taku Izumi <izumi.taku@jp.fujitsu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2fcbca6877
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3bb025d4f7
@ -351,6 +351,107 @@ void fjes_hw_exit(struct fjes_hw *hw)
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fjes_hw_cleanup(hw);
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}
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static enum fjes_dev_command_response_e
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fjes_hw_issue_request_command(struct fjes_hw *hw,
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enum fjes_dev_command_request_type type)
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{
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enum fjes_dev_command_response_e ret = FJES_CMD_STATUS_UNKNOWN;
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union REG_CR cr;
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union REG_CS cs;
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int timeout;
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cr.reg = 0;
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cr.bits.req_start = 1;
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cr.bits.req_code = type;
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wr32(XSCT_CR, cr.reg);
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cr.reg = rd32(XSCT_CR);
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if (cr.bits.error == 0) {
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timeout = FJES_COMMAND_REQ_TIMEOUT * 1000;
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cs.reg = rd32(XSCT_CS);
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while ((cs.bits.complete != 1) && timeout > 0) {
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msleep(1000);
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cs.reg = rd32(XSCT_CS);
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timeout -= 1000;
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}
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if (cs.bits.complete == 1)
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ret = FJES_CMD_STATUS_NORMAL;
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else if (timeout <= 0)
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ret = FJES_CMD_STATUS_TIMEOUT;
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} else {
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switch (cr.bits.err_info) {
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case FJES_CMD_REQ_ERR_INFO_PARAM:
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ret = FJES_CMD_STATUS_ERROR_PARAM;
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break;
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case FJES_CMD_REQ_ERR_INFO_STATUS:
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ret = FJES_CMD_STATUS_ERROR_STATUS;
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break;
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default:
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ret = FJES_CMD_STATUS_UNKNOWN;
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break;
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}
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}
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return ret;
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}
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int fjes_hw_request_info(struct fjes_hw *hw)
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{
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union fjes_device_command_req *req_buf = hw->hw_info.req_buf;
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union fjes_device_command_res *res_buf = hw->hw_info.res_buf;
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enum fjes_dev_command_response_e ret;
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int result;
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memset(req_buf, 0, hw->hw_info.req_buf_size);
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memset(res_buf, 0, hw->hw_info.res_buf_size);
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req_buf->info.length = FJES_DEV_COMMAND_INFO_REQ_LEN;
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res_buf->info.length = 0;
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res_buf->info.code = 0;
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ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_INFO);
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result = 0;
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if (FJES_DEV_COMMAND_INFO_RES_LEN((*hw->hw_info.max_epid)) !=
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res_buf->info.length) {
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result = -ENOMSG;
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} else if (ret == FJES_CMD_STATUS_NORMAL) {
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switch (res_buf->info.code) {
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case FJES_CMD_REQ_RES_CODE_NORMAL:
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result = 0;
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break;
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default:
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result = -EPERM;
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break;
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}
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} else {
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switch (ret) {
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case FJES_CMD_STATUS_UNKNOWN:
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result = -EPERM;
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break;
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case FJES_CMD_STATUS_TIMEOUT:
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result = -EBUSY;
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break;
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case FJES_CMD_STATUS_ERROR_PARAM:
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result = -EPERM;
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break;
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case FJES_CMD_STATUS_ERROR_STATUS:
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result = -EPERM;
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break;
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default:
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result = -EPERM;
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break;
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}
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}
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return result;
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}
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void fjes_hw_set_irqmask(struct fjes_hw *hw,
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enum REG_ICTL_MASK intr_mask, bool mask)
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{
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@ -34,6 +34,12 @@ struct fjes_hw;
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#define EP_BUFFER_INFO_SIZE 4096
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#define FJES_DEVICE_RESET_TIMEOUT ((17 + 1) * 3) /* sec */
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#define FJES_COMMAND_REQ_TIMEOUT (5 + 1) /* sec */
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#define FJES_CMD_REQ_ERR_INFO_PARAM (0x0001)
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#define FJES_CMD_REQ_ERR_INFO_STATUS (0x0002)
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#define FJES_CMD_REQ_RES_CODE_NORMAL (0)
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#define EP_BUFFER_SIZE \
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(((sizeof(union ep_buffer_info) + (128 * (64 * 1024))) \
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@ -50,6 +56,7 @@ struct fjes_hw;
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((size) - sizeof(struct esmem_frame) - \
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(ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
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#define FJES_DEV_COMMAND_INFO_REQ_LEN (4)
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#define FJES_DEV_COMMAND_INFO_RES_LEN(epnum) (8 + 2 * (epnum))
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#define FJES_DEV_COMMAND_SHARE_BUFFER_REQ_LEN(txb, rxb) \
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(24 + (8 * ((txb) / EP_BUFFER_INFO_SIZE + (rxb) / EP_BUFFER_INFO_SIZE)))
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@ -124,6 +131,13 @@ union fjes_device_command_res {
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} stop_trace;
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};
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/* request command type */
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enum fjes_dev_command_request_type {
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FJES_CMD_REQ_INFO = 0x0001,
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FJES_CMD_REQ_SHARE_BUFFER = 0x0002,
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FJES_CMD_REQ_UNSHARE_BUFFER = 0x0004,
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};
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/* parameter for command control */
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struct fjes_device_command_param {
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u32 req_len;
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@ -133,6 +147,15 @@ struct fjes_device_command_param {
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phys_addr_t share_start;
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};
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/* error code for command control */
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enum fjes_dev_command_response_e {
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FJES_CMD_STATUS_UNKNOWN,
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FJES_CMD_STATUS_NORMAL,
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FJES_CMD_STATUS_TIMEOUT,
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FJES_CMD_STATUS_ERROR_PARAM,
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FJES_CMD_STATUS_ERROR_STATUS,
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};
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/* EP buffer information */
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union ep_buffer_info {
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u8 raw[EP_BUFFER_INFO_SIZE];
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@ -243,6 +266,7 @@ struct fjes_hw {
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int fjes_hw_init(struct fjes_hw *);
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void fjes_hw_exit(struct fjes_hw *);
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int fjes_hw_reset(struct fjes_hw *);
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int fjes_hw_request_info(struct fjes_hw *);
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void fjes_hw_init_command_registers(struct fjes_hw *,
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struct fjes_device_command_param *);
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@ -35,6 +35,8 @@
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#define XSCT_DCTL 0x0010 /* Device Control */
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/* Command Control registers */
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#define XSCT_CR 0x0020 /* Command request */
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#define XSCT_CS 0x0024 /* Command status */
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#define XSCT_SHSTSAL 0x0028 /* Share status address Low */
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#define XSCT_SHSTSAH 0x002C /* Share status address High */
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@ -78,6 +80,27 @@ union REG_DCTL {
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__le32 reg;
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};
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/* Command Control registers */
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union REG_CR {
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struct {
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__le32 req_code:16;
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__le32 err_info:14;
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__le32 error:1;
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__le32 req_start:1;
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} bits;
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__le32 reg;
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};
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union REG_CS {
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struct {
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__le32 req_code:16;
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__le32 rsv0:14;
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__le32 busy:1;
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__le32 complete:1;
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} bits;
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__le32 reg;
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};
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enum REG_ICTL_MASK {
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REG_ICTL_MASK_INFO_UPDATE = 1 << 20,
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REG_ICTL_MASK_DEV_STOP_REQ = 1 << 19,
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