forked from luck/tmp_suning_uos_patched
arm64: kernel: make the pen of the secondary a 64-bit unsigned value
Change the prototype of write_pen_release() accordingly and clarify that's holding the hardware id of the secondary that's going to boot. This is in preparation of getting HWIDs parsed from the DT. Signed-off-by: Javi Merino <javi.merino@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -26,6 +26,8 @@
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#define ID_AA64ISAR0_EL1 "id_aa64isar0_el1"
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#define ID_AA64MMFR0_EL1 "id_aa64mmfr0_el1"
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#define INVALID_HWID ULONG_MAX
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#define read_cpuid(reg) ({ \
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u64 __val; \
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asm("mrs %0, " reg : "=r" (__val)); \
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@ -53,7 +53,7 @@
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* where to place its SVC stack
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*/
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struct secondary_data secondary_data;
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volatile unsigned long secondary_holding_pen_release = -1;
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volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
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enum ipi_msg_type {
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IPI_RESCHEDULE,
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@ -70,7 +70,7 @@ static DEFINE_RAW_SPINLOCK(boot_lock);
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* in coherency or not. This is necessary for the hotplug code to work
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* reliably.
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*/
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static void __cpuinit write_pen_release(int val)
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static void __cpuinit write_pen_release(u64 val)
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{
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void *start = (void *)&secondary_holding_pen_release;
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unsigned long size = sizeof(secondary_holding_pen_release);
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@ -105,7 +105,7 @@ static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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if (secondary_holding_pen_release == -1UL)
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if (secondary_holding_pen_release == INVALID_HWID)
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break;
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udelay(10);
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}
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@ -116,7 +116,7 @@ static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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*/
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raw_spin_unlock(&boot_lock);
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return secondary_holding_pen_release != -1 ? -ENOSYS : 0;
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return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
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}
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static DECLARE_COMPLETION(cpu_running);
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@ -190,7 +190,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
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* Let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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write_pen_release(INVALID_HWID);
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/*
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* Synchronise with the boot thread.
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