forked from luck/tmp_suning_uos_patched
sh: Add SH7720 CPU support.
This adds support for the SH7720 (SH3-DSP) CPU. Signed-off by: Markus Brunner <super.firetwister@gmail.com> Signed-off by: Mark Jonas <toertel@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Markus Brunner
Paul Mundt
parent
dfc5ed2a93
commit
3ea6bc3de4
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@ -34,6 +34,7 @@ config EARLY_SCIF_CONSOLE_PORT
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default "0xfffe9800" if CPU_SUBTYPE_SH7206
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default "0xf8420000" if CPU_SUBTYPE_SH7619
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default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
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default "0xa4430000" if CPU_SUBTYPE_SH7720
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default "0xffc30000" if CPU_SUBTYPE_SHX3
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default "0xffe80000" if CPU_SH4
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default "0x00000000"
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@ -12,6 +12,7 @@ config SH_DMA
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config NR_ONCHIP_DMA_CHANNELS
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int
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depends on SH_DMA
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default "6" if CPU_SUBTYPE_SH7720
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default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
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default "12" if CPU_SUBTYPE_SH7780
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default "4"
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@ -24,13 +24,18 @@ static int dmte_irq_map[] = {
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DMTE1_IRQ,
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DMTE2_IRQ,
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DMTE3_IRQ,
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#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7760) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780)
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DMTE4_IRQ,
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DMTE5_IRQ,
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7760) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780)
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DMTE6_IRQ,
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DMTE7_IRQ,
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DMTE7_IRQ,
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#endif
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};
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@ -196,7 +201,8 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan)
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return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
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}
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#ifdef CONFIG_CPU_SUBTYPE_SH7780
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780)
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#define dmaor_read_reg() ctrl_inw(DMAOR)
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#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
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#else
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@ -12,6 +12,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh770x.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o
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# Primary on-chip clocks (common)
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clock-$(CONFIG_CPU_SH3) := clock-sh3.o
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@ -19,5 +20,6 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7705) := clock-sh7705.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7710.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7710.o
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obj-y += $(clock-y)
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@ -81,6 +81,9 @@ int __init detect_cpu_and_cache_system(void)
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#if defined(CONFIG_CPU_SUBTYPE_SH7712)
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current_cpu_data.type = CPU_SH7712;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7720)
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current_cpu_data.type = CPU_SH7720;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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current_cpu_data.type = CPU_SH7705;
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210
arch/sh/kernel/cpu/sh3/setup-sh7720.c
Normal file
210
arch/sh/kernel/cpu/sh3/setup-sh7720.c
Normal file
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@ -0,0 +1,210 @@
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/*
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* SH7720 Setup
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*
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* Copyright (C) 2007 Markus Brunner, Mark Jonas
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*
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* Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
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*
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* Copyright (C) 2006 Paul Mundt
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* Copyright (C) 2006 Jamie Lenehan
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/io.h>
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#include <asm/sci.h>
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#include <asm/rtc.h>
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#define INTC_ICR1 0xA4140010UL
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#define INTC_ICR_IRLM 0x4000
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#define INTC_ICR_IRQ (~INTC_ICR_IRLM)
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xa413fec0,
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.end = 0xa413fec0 + 0x28 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Period IRQ */
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.start = 21,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* Carry IRQ */
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.start = 22,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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/* Alarm IRQ */
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.start = 20,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct sh_rtc_platform_info rtc_info = {
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.capabilities = RTC_CAP_4_DIGIT_YEAR,
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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.dev = {
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.platform_data = &rtc_info,
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},
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};
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xa4430000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 80, 80, 80, 80 },
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}, {
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.mapbase = 0xa4438000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 81, 81, 81, 81 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct platform_device *sh7720_devices[] __initdata = {
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&rtc_device,
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&sci_device,
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};
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static int __init sh7720_devices_setup(void)
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{
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return platform_add_devices(sh7720_devices,
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ARRAY_SIZE(sh7720_devices));
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}
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__initcall(sh7720_devices_setup);
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enum {
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UNUSED = 0,
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/* interrupt sources */
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TMU0, TMU1, TMU2, RTC_ATI, RTC_PRI, RTC_CUI,
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WDT, REF_RCMI, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
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IRQ0, IRQ1, IRQ2, IRQ3,
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USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
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DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3, LCDC, SSL,
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ADC, DMAC2_DEI4, DMAC2_DEI5, USBFI0, USBFI1, CMT,
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SCIF0, SCIF1,
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PINT07, PINT815, TPU0, TPU1, TPU2, TPU3, IIC,
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SIOF0, SIOF1, MMCI0, MMCI1, MMCI2, MMCI3, PCC,
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USBHI, AFEIF,
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H_UDI,
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/* interrupt groups */
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TMU, RTC, SIM, DMAC1, USBFI, DMAC2, USB, TPU, MMC,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480),
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INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0),
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INTC_VECT(SIM_ERI, 0x4e0), INTC_VECT(SIM_RXI, 0x500),
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INTC_VECT(SIM_TXI, 0x520), INTC_VECT(SIM_TEND, 0x540),
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INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
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/* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
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INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800),
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INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840),
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INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900),
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INTC_VECT(SSL, 0x980), INTC_VECT(USBFI0, 0xa20),
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INTC_VECT(USBFI1, 0xa40), INTC_VECT(USBHI, 0xa60),
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INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0),
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INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
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INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
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INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
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INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU0, 0xd80),
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INTC_VECT(TPU1, 0xda0), INTC_VECT(TPU2, 0xdc0),
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INTC_VECT(TPU3, 0xde0), INTC_VECT(IIC, 0xe00),
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INTC_VECT(MMCI0, 0xe80), INTC_VECT(MMCI1, 0xea0),
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INTC_VECT(MMCI2, 0xec0), INTC_VECT(MMCI3, 0xee0),
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INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
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INTC_VECT(AFEIF, 0xfe0),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(TMU, TMU0, TMU1, TMU2),
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INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
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INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
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INTC_GROUP(DMAC1, DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3),
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INTC_GROUP(USBFI, USBFI0, USBFI1),
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INTC_GROUP(DMAC2, DMAC2_DEI4, DMAC2_DEI5),
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INTC_GROUP(TPU, TPU0, TPU1, TPU2, TPU3),
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INTC_GROUP(MMC, MMCI0, MMCI1, MMCI2, MMCI3),
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};
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static struct intc_prio priorities[] __initdata = {
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INTC_PRIO(SCIF0, 2),
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INTC_PRIO(SCIF1, 2),
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INTC_PRIO(DMAC1, 1),
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INTC_PRIO(DMAC2, 1),
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INTC_PRIO(RTC, 2),
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INTC_PRIO(TMU, 2),
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INTC_PRIO(TPU, 2),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
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{ 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
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{ 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
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{ 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
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{ 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
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{ 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
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{ 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
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{ 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
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{ 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups,
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priorities, NULL, prio_registers, NULL);
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static struct intc_sense_reg sense_registers[] __initdata = {
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{ INTC_ICR1, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
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};
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static struct intc_vect vectors_irq[] __initdata = {
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INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
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INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
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INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
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};
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static DECLARE_INTC_DESC(intc_irq_desc, "sh7720-irq", vectors_irq,
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NULL, priorities, NULL, prio_registers, sense_registers);
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void __init plat_irq_setup_pins(int mode)
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{
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switch (mode) {
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case IRQ_MODE_IRQ:
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ctrl_outw(ctrl_inw(INTC_ICR1) & INTC_ICR_IRQ, INTC_ICR1);
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register_intc_controller(&intc_irq_desc);
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break;
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default:
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BUG();
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}
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}
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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}
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@ -13,6 +13,7 @@
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#include <linux/tty.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#ifdef CONFIG_SH_STANDARD_BIOS
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#include <asm/sh_bios.h>
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@ -62,6 +63,18 @@ static struct console bios_console = {
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#include <linux/serial_core.h>
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#include "../../../drivers/serial/sh-sci.h"
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#if defined(CONFIG_CPU_SUBTYPE_SH7720)
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#define EPK_SCSMR_VALUE 0x000
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#define EPK_SCBRR_VALUE 0x00C
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#define EPK_FIFO_SIZE 64
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#define EPK_FIFO_BITS (0x7f00 >> 8)
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#else
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#define EPK_FIFO_SIZE 16
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#define EPK_FIFO_BITS (0x1f00 >> 8)
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#endif
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static struct uart_port scif_port = {
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.mapbase = CONFIG_EARLY_SCIF_CONSOLE_PORT,
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.membase = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT,
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@ -69,7 +82,7 @@ static struct uart_port scif_port = {
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static void scif_sercon_putc(int c)
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{
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while (((sci_in(&scif_port, SCFDR) & 0x1f00 >> 8) == 16))
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while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE))
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;
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sci_out(&scif_port, SCxTDR, c);
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@ -105,7 +118,22 @@ static struct console scif_console = {
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.index = -1,
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};
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#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_STANDARD_BIOS)
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#if !defined(CONFIG_SH_STANDARD_BIOS)
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#if defined(CONFIG_CPU_SUBTYPE_SH7720)
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static void scif_sercon_init(char *s)
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{
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sci_out(&scif_port, SCSCR, 0x0000); /* clear TE and RE */
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sci_out(&scif_port, SCFCR, 0x4006); /* reset */
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sci_out(&scif_port, SCSCR, 0x0000); /* select internal clock */
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sci_out(&scif_port, SCSMR, EPK_SCSMR_VALUE);
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sci_out(&scif_port, SCBRR, EPK_SCBRR_VALUE);
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mdelay(1); /* wait 1-bit time */
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sci_out(&scif_port, SCFCR, 0x0030); /* TTRG=b'11 */
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sci_out(&scif_port, SCSCR, 0x0030); /* TE, RE */
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}
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#elif defined(CONFIG_CPU_SH4)
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#define DEFAULT_BAUD 115200
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/*
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* Simple SCIF init, primarily aimed at SH7750 and other similar SH-4
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@ -146,7 +174,8 @@ static void scif_sercon_init(char *s)
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ctrl_outw(0, scif_port.mapbase + 36);
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ctrl_outw(0x30, scif_port.mapbase + 8);
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}
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#endif /* CONFIG_CPU_SH4 && !CONFIG_SH_STANDARD_BIOS */
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#endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */
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#endif /* !defined(CONFIG_SH_STANDARD_BIOS) */
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#endif /* CONFIG_EARLY_SCIF_CONSOLE */
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/*
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@ -186,7 +215,8 @@ int __init setup_early_printk(char *buf)
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if (!strncmp(buf, "serial", 6)) {
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early_console = &scif_console;
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#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_STANDARD_BIOS)
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#if (defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720)) && \
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!defined(CONFIG_SH_STANDARD_BIOS)
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scif_sercon_init(buf + 6);
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#endif
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}
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@ -279,7 +279,7 @@ static const char *cpu_name[] = {
|
|||
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
|
||||
[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
|
||||
[CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
|
||||
[CPU_SH7712] = "SH7712",
|
||||
[CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
|
||||
[CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750",
|
||||
[CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
|
||||
[CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
|
||||
|
|
|
|||
|
|
@ -173,7 +173,8 @@ static int tmu_timer_init(void)
|
|||
|
||||
tmu_timer_stop();
|
||||
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7785) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
|
||||
|
|
|
|||
|
|
@ -111,6 +111,14 @@ config CPU_SUBTYPE_SH7712
|
|||
help
|
||||
Select SH7712 if you have a SH3-DSP SH7712 CPU.
|
||||
|
||||
config CPU_SUBTYPE_SH7720
|
||||
bool "Support SH7720 processor"
|
||||
select CPU_SH3
|
||||
select CPU_HAS_INTC_IRQ
|
||||
select CPU_HAS_DSP
|
||||
help
|
||||
Select SH7720 if you have a SH3-DSP SH7720 CPU.
|
||||
|
||||
# SH-4 Processor Support
|
||||
|
||||
config CPU_SUBTYPE_SH7750
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
|
||||
*
|
||||
* Copyright (C) 2002 - 2006 Paul Mundt
|
||||
* Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
|
||||
*
|
||||
* based off of the old drivers/char/sh-sci.c by:
|
||||
*
|
||||
|
|
@ -301,6 +302,38 @@ static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
|
|||
}
|
||||
sci_out(port, SCFCR, fcr_val);
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
||||
{
|
||||
unsigned int fcr_val = 0;
|
||||
unsigned short data;
|
||||
|
||||
if (cflag & CRTSCTS) {
|
||||
/* enable RTS/CTS */
|
||||
if (port->mapbase == 0xa4430000) { /* SCIF0 */
|
||||
/* Clear PTCR bit 9-2; enable all scif pins but sck */
|
||||
data = ctrl_inw(PORT_PTCR);
|
||||
ctrl_outw((data & 0xfc03), PORT_PTCR);
|
||||
} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
|
||||
/* Clear PVCR bit 9-2 */
|
||||
data = ctrl_inw(PORT_PVCR);
|
||||
ctrl_outw((data & 0xfc03), PORT_PVCR);
|
||||
}
|
||||
fcr_val |= SCFCR_MCE;
|
||||
} else {
|
||||
if (port->mapbase == 0xa4430000) { /* SCIF0 */
|
||||
/* Clear PTCR bit 5-2; enable only tx and rx */
|
||||
data = ctrl_inw(PORT_PTCR);
|
||||
ctrl_outw((data & 0xffc3), PORT_PTCR);
|
||||
} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
|
||||
/* Clear PVCR bit 5-2 */
|
||||
data = ctrl_inw(PORT_PVCR);
|
||||
ctrl_outw((data & 0xffc3), PORT_PVCR);
|
||||
}
|
||||
}
|
||||
sci_out(port, SCFCR, fcr_val);
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_CPU_SH3)
|
||||
/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
|
||||
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
||||
|
|
|
|||
|
|
@ -10,19 +10,19 @@
|
|||
* Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
|
||||
* Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
|
||||
* Removed SH7300 support (Jul 2007).
|
||||
* Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
|
||||
*/
|
||||
#include <linux/serial_core.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if defined(__H8300H__) || defined(__H8300S__)
|
||||
#include <asm/gpio.h>
|
||||
|
||||
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
#include <asm/regs306x.h>
|
||||
#endif
|
||||
#if defined(CONFIG_H8S2678)
|
||||
#include <asm/regs267x.h>
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
|
|
@ -46,6 +46,10 @@
|
|||
*/
|
||||
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define SCIF_ONLY
|
||||
#define SCIF_ORER 0x0200 /* overrun error bit */
|
||||
#elif defined(CONFIG_SH_RTS7751R2D)
|
||||
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
|
|
@ -217,7 +221,8 @@
|
|||
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
#define SCIF_ORER 0x0200
|
||||
#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
|
||||
#define SCIF_RFDC_MASK 0x007f
|
||||
|
|
@ -254,7 +259,8 @@
|
|||
# define SCxSR_FER(port) SCIF_FER
|
||||
# define SCxSR_PER(port) SCIF_PER
|
||||
# define SCxSR_BRK(port) SCIF_BRK
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
|
||||
# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
|
||||
# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
|
||||
|
|
@ -362,7 +368,8 @@
|
|||
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
#define SCIF_FNS(name, scif_offset, scif_size) \
|
||||
CPU_SCIF_FNS(name, scif_offset, scif_size)
|
||||
#else
|
||||
|
|
@ -388,7 +395,8 @@
|
|||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
|
||||
SCIF_FNS(SCSMR, 0x00, 16)
|
||||
SCIF_FNS(SCBRR, 0x04, 8)
|
||||
|
|
@ -510,7 +518,15 @@ static inline void set_sh771x_scif_pfc(struct uart_port *port)
|
|||
return;
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xa4430000)
|
||||
return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
|
||||
else if (port->mapbase == 0xa4438000)
|
||||
return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
|
||||
|
|
@ -692,7 +708,8 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
|
||||
|
|
|
|||
|
|
@ -26,7 +26,9 @@
|
|||
#define CCR_CACHE_ENABLE CCR_CACHE_CE
|
||||
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
#define CCR3 0xa40000b4
|
||||
#define CCR_CACHE_16KB 0x00010000
|
||||
#define CCR_CACHE_32KB 0x00020000
|
||||
|
|
|
|||
|
|
@ -1,7 +1,20 @@
|
|||
#ifndef __ASM_CPU_SH3_DMA_H
|
||||
#define __ASM_CPU_SH3_DMA_H
|
||||
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
#define SH_DMAC_BASE 0xa4010020
|
||||
|
||||
#define DMTE0_IRQ 48
|
||||
#define DMTE1_IRQ 49
|
||||
#define DMTE2_IRQ 50
|
||||
#define DMTE3_IRQ 51
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMTE5_IRQ 77
|
||||
|
||||
#else
|
||||
#define SH_DMAC_BASE 0xa4000020
|
||||
#endif
|
||||
|
||||
/* Definitions for the SuperH DMAC */
|
||||
#define TM_BURST 0x00000020
|
||||
|
|
|
|||
|
|
@ -27,12 +27,13 @@
|
|||
#define TRA 0xffffffd0
|
||||
#define EXPEVT 0xffffffd4
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7712) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
|
||||
#else
|
||||
#define INTEVT 0xffffffd8
|
||||
|
|
|
|||
|
|
@ -23,11 +23,13 @@
|
|||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7727)
|
||||
#define TMU_TOCR 0xfffffe90 /* Byte access */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
#define TMU_012_TSTR 0xa412fe92 /* Byte access */
|
||||
|
||||
#define TMU0_TCOR 0xa412fe94 /* Long access */
|
||||
|
|
@ -56,7 +58,8 @@
|
|||
#define TMU2_TCOR 0xfffffeac /* Long access */
|
||||
#define TMU2_TCNT 0xfffffeb0 /* Long access */
|
||||
#define TMU2_TCR 0xfffffeb4 /* Word access */
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7727)
|
||||
#define TMU2_TCPR2 0xfffffeb8 /* Long access */
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,7 +11,8 @@
|
|||
#ifndef __ASM_CPU_SH3_UBC_H
|
||||
#define __ASM_CPU_SH3_UBC_H
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
#define UBC_BARA 0xa4ffffb0
|
||||
#define UBC_BAMRA 0xa4ffffb4
|
||||
#define UBC_BBRA 0xa4ffffb8
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ enum cpu_type {
|
|||
CPU_SH7705, CPU_SH7706, CPU_SH7707,
|
||||
CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
|
||||
CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
|
||||
CPU_SH7729,
|
||||
CPU_SH7720, CPU_SH7729,
|
||||
|
||||
/* SH-4 types */
|
||||
CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user