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ARM: SoC non-urgent fixes for v4.10

Browse Source 
As usual, we queue up a few fixes that don't seem urgent enough to go in
 through -rc, or that just came a little too late given their size.
 
 The zx fixes make the platform finally boot on real hardware, the
 davinci and imx31 get the DT support working better for some of
 the machines that are still normally used with classic board files.
 One tegra fix is important for new bootloader versions, but the
 bug has been around for a while without anyone noticing.
 
 The other changes are mostly cosmetic.
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Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-urgent fixes from Arnd Bergmann:
 "As usual, we queue up a few fixes that don't seem urgent enough to go
  in through -rc, or that just came a little too late given their size.

  The zx fixes make the platform finally boot on real hardware, the
  davinci and imx31 get the DT support working better for some of the
  machines that are still normally used with classic board files. One
  tegra fix is important for new bootloader versions, but the bug has
  been around for a while without anyone noticing.

  The other changes are mostly cosmetic"

* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
  arm64: tegra: Add missing Smaug revision
  arm64: tegra: Add VDD_GPU regulator to Jetson TX1
  arm64: dts: zte: clean up gic-v3 redistributor properties
  arm64: dts: zx: Fix gic GICR property
  bus: vexpress-config: fix device reference leak
  soc: ti: qmss: fix the case when !SMP
  ARM: lpc32xx: drop duplicate header device.h
  ARM: ixp4xx: drop duplicate header gpio.h
  ARM: socfpga: fix spelling mistake in error message
  ARM: dts: imx6q-cm-fx6: fix fec pinctrl
  ARM: dts: imx7d-pinfunc: fix UART pinmux defines
  ARM: dts: imx6qp: correct LDB clock inputs
  ARM: OMAP2+: pm-debug: Use seq_putc() in two functions
  ARM: OMAP2+: Remove the omapdss_early_init_of() function
  mfd: tps65217: Fix mismatched interrupt number
  ARM: zx: Fix error handling
  ARM: spear: Fix error handling
  ARM: davinci: da850: Fix pwm name matching
  ARM: clk: imx31: properly init clocks for machines with DT
  clk: imx31: fix rewritten input argument of mx31_clocks_init()
  ...
This commit is contained in:
Linus Torvalds 2016-12-15 15:15:13 -08:00
commit 3ec5e8d82b
25 changed files with 140 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/clock/imx31-clock.txt
View File

@ -77,7 +77,7 @@ Examples:
clks: ccm@53f80000{
compatible = "fsl,imx31-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <0 31 0x04 0 53 0x04>;
interrupts = <31>, <53>;
#clock-cells = <1>;
};

14
arch/arm/boot/dts/imx31.dtsi
View File

@ -118,13 +118,6 @@ iim: iim@5001c000 {
interrupts = <19>;
clocks = <&clks 25>;
};
clks: ccm@53f80000{
compatible = "fsl,imx31-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <0 31 0x04 0 53 0x04>;
#clock-cells = <1>;
};
};
aips@53f00000 { /* AIPS2 */
@ -134,6 +127,13 @@ aips@53f00000 { /* AIPS2 */
reg = <0x53f00000 0x100000>;
ranges;
clks: ccm@53f80000{
compatible = "fsl,imx31-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>, <53>;
#clock-cells = <1>;
};
gpt: timer@53f90000 {
compatible = "fsl,imx31-gpt";
reg = <0x53f90000 0x4000>;

1
arch/arm/boot/dts/imx6q-cm-fx6.dts
View File

@ -183,7 +183,6 @@ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};

10
arch/arm/boot/dts/imx6qp.dtsi
View File

@ -87,3 +87,13 @@ pcie: pcie@0x01000000 {
};
};
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
"di0", "di1";
};

12
arch/arm/boot/dts/imx7d-pinfunc.h
View File

@ -43,26 +43,30 @@
#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
#define MX7D_PAD_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
#define MX7D_PAD_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5
#define MX7D_PAD_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
#define MX7D_PAD_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
#define MX7D_PAD_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
#define MX7D_PAD_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5
#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1

48
arch/arm/mach-davinci/da850.c
View File

@ -424,6 +424,16 @@ static struct clk ehrpwm_clk = {
.gpsc = 1,
};
static struct clk ehrpwm0_clk = {
.name = "ehrpwm0",
.parent = &ehrpwm_clk,
};
static struct clk ehrpwm1_clk = {
.name = "ehrpwm1",
.parent = &ehrpwm_clk,
};
#define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
static void ehrpwm_tblck_enable(struct clk *clk)
@ -451,6 +461,16 @@ static struct clk ehrpwm_tbclk = {
.clk_disable = ehrpwm_tblck_disable,
};
static struct clk ehrpwm0_tbclk = {
.name = "ehrpwm0_tbclk",
.parent = &ehrpwm_tbclk,
};
static struct clk ehrpwm1_tbclk = {
.name = "ehrpwm1_tbclk",
.parent = &ehrpwm_tbclk,
};
static struct clk ecap_clk = {
.name = "ecap",
.parent = &async3_clk,
@ -458,6 +478,21 @@ static struct clk ecap_clk = {
.gpsc = 1,
};
static struct clk ecap0_clk = {
.name = "ecap0_clk",
.parent = &ecap_clk,
};
static struct clk ecap1_clk = {
.name = "ecap1_clk",
.parent = &ecap_clk,
};
static struct clk ecap2_clk = {
.name = "ecap2_clk",
.parent = &ecap_clk,
};
static struct clk_lookup da850_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "pll0", &pll0_clk),
@ -510,9 +545,16 @@ static struct clk_lookup da850_clks[] = {
CLK("vpif", NULL, &vpif_clk),
CLK("ahci_da850", NULL, &sata_clk),
CLK("davinci-rproc.0", NULL, &dsp_clk),
CLK("ehrpwm", "fck", &ehrpwm_clk),
CLK("ehrpwm", "tbclk", &ehrpwm_tbclk),
CLK("ecap", "fck", &ecap_clk),
CLK(NULL, NULL, &ehrpwm_clk),
CLK("ehrpwm.0", "fck", &ehrpwm0_clk),
CLK("ehrpwm.1", "fck", &ehrpwm1_clk),
CLK(NULL, NULL, &ehrpwm_tbclk),
CLK("ehrpwm.0", "tbclk", &ehrpwm0_tbclk),
CLK("ehrpwm.1", "tbclk", &ehrpwm1_tbclk),
CLK(NULL, NULL, &ecap_clk),
CLK("ecap.0", "fck", &ecap0_clk),
CLK("ecap.1", "fck", &ecap1_clk),
CLK("ecap.2", "fck", &ecap2_clk),
CLK(NULL, NULL, NULL),
};

10
arch/arm/mach-davinci/da8xx-dt.c
View File

@ -23,11 +23,11 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("ti,davinci-i2c", 0x01e28000, "i2c_davinci.2", NULL),
OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "davinci-wdt", NULL),
OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL),
OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm", NULL),
OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm", NULL),
OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap", NULL),
OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL),
OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL),
OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm.0", NULL),
OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm.1", NULL),
OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap.0", NULL),
OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap.1", NULL),
OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap.2", NULL),
OF_DEV_AUXDATA("ti,da830-spi", 0x01c41000, "spi_davinci.0", NULL),
OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL),
OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL),

1
arch/arm/mach-imx/common.h
View File

@ -43,7 +43,6 @@ int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref);
int mx35_clocks_init(void);
int mx31_clocks_init_dt(void);
struct platform_device *mxc_register_gpio(char *name, int id,
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
void mxc_set_cpu_type(unsigned int type);

6
arch/arm/mach-imx/imx31-dt.c
View File

@ -23,11 +23,6 @@ static const char * const imx31_dt_board_compat[] __initconst = {
NULL
};
static void __init imx31_dt_timer_init(void)
{
mx31_clocks_init_dt();
}
/* FIXME: replace with DT binding */
static const struct resource imx31_rnga_res[] __initconst = {
DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
@ -43,7 +38,6 @@ DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
.init_time = imx31_dt_timer_init,
.init_machine = imx31_dt_mach_init,
.dt_compat = imx31_dt_board_compat,
MACHINE_END

1
arch/arm/mach-ixp4xx/dsmg600-setup.c
View File

@ -26,7 +26,6 @@
#include <linux/reboot.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/gpio.h>
#include <mach/hardware.h>

1
arch/arm/mach-lpc32xx/phy3250.c
View File

@ -23,7 +23,6 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>

2
arch/arm/mach-omap2/board-generic.c
View File

@ -30,8 +30,6 @@ static const struct of_device_id omap_dt_match_table[] __initconst = {
static void __init omap_generic_init(void)
{
omapdss_early_init_of();
pdata_quirks_init(omap_dt_match_table);
omapdss_init_of();

1
arch/arm/mach-omap2/common.h
View File

@ -332,7 +332,6 @@ extern int omap_dss_reset(struct omap_hwmod *);
int omap_clk_init(void);
int __init omapdss_init_of(void);
void __init omapdss_early_init_of(void);
#endif /* __ASSEMBLER__ */
#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */

5
arch/arm/mach-omap2/display.c
View File

@ -565,11 +565,6 @@ int omap_dss_reset(struct omap_hwmod *oh)
return r;
}
void __init omapdss_early_init_of(void)
{
}
static const char * const omapdss_compat_names[] __initconst = {
"ti,omap2-dss",
"ti,omap3-dss",

5
arch/arm/mach-omap2/pm-debug.c
View File

@ -114,8 +114,7 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1,
pwrdm->ret_mem_off_counter[i]);
seq_printf(s, "\n");
seq_putc(s, '\n');
return 0;
}
@ -138,7 +137,7 @@ static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
pwrdm->state_timer[i]);
seq_printf(s, "\n");
seq_putc(s, '\n');
return 0;
}

2
arch/arm/mach-socfpga/l2_cache.c
View File

@ -74,7 +74,7 @@ void socfpga_init_arria10_l2_ecc(void)
}
if (!sys_manager_base_addr) {
pr_err("System Mananger not mapped for L2 ECC\n");
pr_err("System Manager not mapped for L2 ECC\n");
goto exit;
}
/* Clear any pending IRQs */

2
arch/arm/mach-spear/time.c
View File

@ -233,7 +233,7 @@ void __init spear_setup_of_timer(void)
}
gpt_clk = clk_get_sys("gpt0", NULL);
if (!gpt_clk) {
if (IS_ERR(gpt_clk)) {
pr_err("%s:couldn't get clk for gpt\n", __func__);
goto err_iomap;
}

2
arch/arm/mach-zx/zx296702-pm-domain.c
View File

@ -169,7 +169,7 @@ static int zx296702_pd_probe(struct platform_device *pdev)
}
pcubase = devm_ioremap_resource(&pdev->dev, res);
if (!pcubase) {
if (IS_ERR(pcubase)) {
dev_err(&pdev->dev, "ioremap fail.\n");
return -EIO;
}

18
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
View File

@ -21,6 +21,10 @@ memory {
reg = <0x0 0x80000000 0x1 0x0>;
};
gpu@57000000 {
vdd-supply = <&vdd_gpu>;
};
/* debug port */
serial@70006000 {
status = "okay";
@ -291,4 +295,18 @@ clk32k_in: clock@0 {
clock-frequency = <32768>;
};
};
regulators {
vdd_gpu: regulator@100 {
compatible = "pwm-regulator";
reg = <100>;
pwms = <&pwm 1 4880>;
regulator-name = "VDD_GPU";
regulator-min-microvolt = <710000>;
regulator-max-microvolt = <1320000>;
enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
regulator-ramp-delay = <80>;
regulator-enable-ramp-delay = <1000>;
};
};
};

3
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
View File

@ -11,7 +11,8 @@ / {
compatible = "google,smaug-rev8", "google,smaug-rev7",
"google,smaug-rev6", "google,smaug-rev5",
"google,smaug-rev4", "google,smaug-rev3",
"google,smaug-rev1", "google,smaug", "nvidia,tegra210";
"google,smaug-rev2", "google,smaug-rev1",
"google,smaug", "nvidia,tegra210";
aliases {
serial0 = &uarta;

9
arch/arm64/boot/dts/zte/zx296718.dtsi
View File

@ -239,16 +239,9 @@ gic: interrupt-controller@2a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
#redistributor-regions = <6>;
redistributor-stride = <0x0 0x40000>;
interrupt-controller;
reg = <0x02a00000 0x10000>,
<0x02b00000 0x20000>,
<0x02b20000 0x20000>,
<0x02b40000 0x20000>,
<0x02b60000 0x20000>,
<0x02b80000 0x20000>,
<0x02ba0000 0x20000>;
<0x02b00000 0xc0000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};

7
drivers/bus/vexpress-config.c
View File

@ -171,6 +171,7 @@ static int vexpress_config_populate(struct device_node *node)
{
struct device_node *bridge;
struct device *parent;
int ret;
bridge = of_parse_phandle(node, "arm,vexpress,config-bridge", 0);
if (!bridge)
@ -182,7 +183,11 @@ static int vexpress_config_populate(struct device_node *node)
if (WARN_ON(!parent))
return -ENODEV;
return of_platform_populate(node, NULL, NULL, parent);
ret = of_platform_populate(node, NULL, NULL, parent);
put_device(parent);
return ret;
}
static int __init vexpress_config_init(void)

52
drivers/clk/imx/clk-imx31.c
View File

@ -21,6 +21,7 @@
#include <linux/io.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <soc/imx/revision.h>
#include <soc/imx/timer.h>
#include <asm/irq.h>
@ -72,14 +73,8 @@ static struct clk ** const uart_clks[] __initconst = {
NULL
};
static void __init _mx31_clocks_init(unsigned long fref)
static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref)
{
void __iomem *base;
struct device_node *np;
base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K);
BUG_ON(!base);
clk[dummy] = imx_clk_fixed("dummy", 0);
clk[ckih] = imx_clk_fixed("ckih", fref);
clk[ckil] = imx_clk_fixed("ckil", 32768);
@ -147,21 +142,17 @@ static void __init _mx31_clocks_init(unsigned long fref)
clk_prepare_enable(clk[iim_gate]);
mx31_revision();
clk_disable_unprepare(clk[iim_gate]);
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
if (np) {
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
}
int __init mx31_clocks_init(void)
int __init mx31_clocks_init(unsigned long fref)
{
u32 fref = 26000000; /* default */
void __iomem *base;
_mx31_clocks_init(fref);
base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K);
if (!base)
panic("%s: failed to map registers\n", __func__);
_mx31_clocks_init(base, fref);
clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
@ -224,22 +215,31 @@ int __init mx31_clocks_init(void)
return 0;
}
int __init mx31_clocks_init_dt(void)
static void __init mx31_clocks_init_dt(struct device_node *np)
{
struct device_node *np;
struct device_node *osc_np;
u32 fref = 26000000; /* default */
void __iomem *ccm;
for_each_compatible_node(np, NULL, "fixed-clock") {
if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
for_each_compatible_node(osc_np, NULL, "fixed-clock") {
if (!of_device_is_compatible(osc_np, "fsl,imx-osc26m"))
continue;
if (!of_property_read_u32(np, "clock-frequency", &fref)) {
of_node_put(np);
if (!of_property_read_u32(osc_np, "clock-frequency", &fref)) {
of_node_put(osc_np);
break;
}
}
_mx31_clocks_init(fref);
ccm = of_iomap(np, 0);
if (!ccm)
panic("%s: failed to map registers\n", __func__);
return 0;
_mx31_clocks_init(ccm, fref);
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
CLK_OF_DECLARE(imx31_ccm, "fsl,imx31-ccm", mx31_clocks_init_dt);

2
drivers/soc/ti/knav_qmss_queue.c
View File

@ -1228,7 +1228,7 @@ static int knav_setup_queue_range(struct knav_device *kdev,
range->num_irqs++;
if (oirq.args_count == 3)
if (IS_ENABLED(CONFIG_SMP) && oirq.args_count == 3)
range->irqs[i].cpu_map =
(oirq.args[2] & 0x0000ff00) >> 8;
}

11
include/linux/mfd/tps65217.h
View File

@ -234,12 +234,11 @@ struct tps65217_bl_pdata {
int dft_brightness;
};
enum tps65217_irq_type {
TPS65217_IRQ_PB,
TPS65217_IRQ_AC,
TPS65217_IRQ_USB,
TPS65217_NUM_IRQ
};
/* Interrupt numbers */
#define TPS65217_IRQ_USB 0
#define TPS65217_IRQ_AC 1
#define TPS65217_IRQ_PB 2
#define TPS65217_NUM_IRQ 3
/**
* struct tps65217_board - packages regulator init data