forked from luck/tmp_suning_uos_patched
ARM: dts: zynq: Add SDHCI nodes
Add nodes for the Arasan SDHCI controller to Zynq dts files. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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4dd18edc01
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@ -102,6 +102,26 @@ gem1: ethernet@e000c000 {
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clock-names = "pclk", "hclk", "tx_clk";
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};
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sdhci0: ps7-sdhci@e0100000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 21>, <&clkc 32>;
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interrupt-parent = <&intc>;
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interrupts = <0 24 4>;
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reg = <0xe0100000 0x1000>;
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} ;
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sdhci1: ps7-sdhci@e0101000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 22>, <&clkc 33>;
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interrupt-parent = <&intc>;
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interrupts = <0 47 4>;
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reg = <0xe0101000 0x1000>;
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} ;
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slcr: slcr@f8000000 {
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compatible = "xlnx,zynq-slcr";
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reg = <0xF8000000 0x1000>;
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@ -34,6 +34,10 @@ &gem0 {
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phy-mode = "rgmii";
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};
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&sdhci0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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@ -35,6 +35,10 @@ &gem0 {
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phy-mode = "rgmii";
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};
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&sdhci0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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@ -35,6 +35,10 @@ &gem0 {
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phy-mode = "rgmii";
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};
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&sdhci0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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