forked from luck/tmp_suning_uos_patched
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle: "Another round of MIPS fixes for 4.2. No area does particularly stand out but we have a two unpleasant ones: - Kernel ptes are marked with a global bit which allows the kernel to share kernel TLB entries between all processes. For this to work both entries of an adjacent even/odd pte pair need to have the global bit set. There has been a subtle race in setting the other entry's global bit since ~ 2000 but it take particularly pathological workloads that essentially do mostly vmalloc/vfree to trigger this. This pull request fixes the 64-bit case but leaves the case of 32 bit CPUs with 64 bit ptes unsolved for now. The unfixed cases affect hardware that is not available in the field yet. - Instruction emulation requires loading instructions from user space but the current fast but simplistic approach will fail on pages that are PROT_EXEC but !PROT_READ. For this reason we temporarily do not permit this permission and will map pages with PROT_EXEC | PROT_READ. The remainder of this pull request is more or less across the field and the short log explains them well" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: Make set_pte() SMP safe. MIPS: Replace add and sub instructions in relocate_kernel.S with addiu MIPS: Flush RPS on kernel entry with EVA Revert "MIPS: BCM63xx: Provide a plat_post_dma_flush hook" MIPS: BMIPS: Delete unused Kconfig symbol MIPS: Export get_c0_perfcount_int() MIPS: show_stack: Fix stack trace with EVA MIPS: do_mcheck: Fix kernel code dump with EVA MIPS: SMP: Don't increment irq_count multiple times for call function IPIs MIPS: Partially disable RIXI support. MIPS: Handle page faults of executable but unreadable pages correctly. MIPS: Malta: Don't reinitialise RTC MIPS: unaligned: Fix build error on big endian R6 kernels MIPS: Fix sched_getaffinity with MT FPAFF enabled MIPS: Fix build with CONFIG_OF=y for non OF-enabled targets CPUFREQ: Loongson2: Fix broken build due to incorrect include.
This commit is contained in:
commit
3fbdc37956
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@ -151,7 +151,6 @@ config BMIPS_GENERIC
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select BCM7120_L2_IRQ
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select BRCMSTB_L2_IRQ
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select IRQ_MIPS_CPU
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select RAW_IRQ_ACCESSORS
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select DMA_NONCOHERENT
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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|
|
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@ -190,6 +190,7 @@ int get_c0_perfcount_int(void)
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{
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return ATH79_MISC_IRQ(5);
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}
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EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
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unsigned int get_c0_compare_int(void)
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{
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|
|
|
@ -42,7 +42,7 @@ static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
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cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
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if (action & SMP_CALL_FUNCTION)
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smp_call_function_interrupt();
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generic_smp_call_function_interrupt();
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if (action & SMP_RESCHEDULE_YOURSELF)
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scheduler_ipi();
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|
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@ -1,10 +0,0 @@
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#ifndef __ASM_MACH_BCM63XX_DMA_COHERENCE_H
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#define __ASM_MACH_BCM63XX_DMA_COHERENCE_H
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#include <asm/bmips.h>
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#define plat_post_dma_flush bmips_post_dma_flush
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#include <asm/mach-generic/dma-coherence.h>
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#endif /* __ASM_MACH_BCM63XX_DMA_COHERENCE_H */
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@ -182,8 +182,39 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
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* Make sure the buddy is global too (if it's !none,
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* it better already be global)
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*/
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#ifdef CONFIG_SMP
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/*
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* For SMP, multiple CPUs can race, so we need to do
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* this atomically.
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*/
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#ifdef CONFIG_64BIT
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#define LL_INSN "lld"
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#define SC_INSN "scd"
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#else /* CONFIG_32BIT */
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#define LL_INSN "ll"
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#define SC_INSN "sc"
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#endif
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unsigned long page_global = _PAGE_GLOBAL;
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unsigned long tmp;
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__asm__ __volatile__ (
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" .set push\n"
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" .set noreorder\n"
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"1: " LL_INSN " %[tmp], %[buddy]\n"
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" bnez %[tmp], 2f\n"
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" or %[tmp], %[tmp], %[global]\n"
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" " SC_INSN " %[tmp], %[buddy]\n"
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" beqz %[tmp], 1b\n"
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" nop\n"
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"2:\n"
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" .set pop"
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: [buddy] "+m" (buddy->pte),
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[tmp] "=&r" (tmp)
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: [global] "r" (page_global));
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#else /* !CONFIG_SMP */
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if (pte_none(*buddy))
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pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL;
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#endif /* CONFIG_SMP */
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}
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#endif
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}
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|
|
|
@ -83,8 +83,6 @@ static inline void __cpu_die(unsigned int cpu)
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extern void play_dead(void);
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#endif
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extern asmlinkage void smp_call_function_interrupt(void);
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static inline void arch_send_call_function_single_ipi(int cpu)
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{
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extern struct plat_smp_ops *mp_ops; /* private */
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|
|
|
@ -152,6 +152,31 @@
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.set noreorder
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bltz k0, 8f
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move k1, sp
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#ifdef CONFIG_EVA
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/*
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* Flush interAptiv's Return Prediction Stack (RPS) by writing
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* EntryHi. Toggling Config7.RPS is slower and less portable.
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*
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* The RPS isn't automatically flushed when exceptions are
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* taken, which can result in kernel mode speculative accesses
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* to user addresses if the RPS mispredicts. That's harmless
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* when user and kernel share the same address space, but with
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* EVA the same user segments may be unmapped to kernel mode,
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* even containing sensitive MMIO regions or invalid memory.
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*
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* This can happen when the kernel sets the return address to
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* ret_from_* and jr's to the exception handler, which looks
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* more like a tail call than a function call. If nested calls
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* don't evict the last user address in the RPS, it will
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* mispredict the return and fetch from a user controlled
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* address into the icache.
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*
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* More recent EVA-capable cores with MAAR to restrict
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* speculative accesses aren't affected.
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*/
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MFC0 k0, CP0_ENTRYHI
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MTC0 k0, CP0_ENTRYHI
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#endif
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.set reorder
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/* Called from user mode, new stack. */
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get_saved_sp
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|
|
|
@ -154,7 +154,7 @@ asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len,
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unsigned long __user *user_mask_ptr)
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{
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unsigned int real_len;
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cpumask_t mask;
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cpumask_t allowed, mask;
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int retval;
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struct task_struct *p;
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|
@ -173,7 +173,8 @@ asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len,
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if (retval)
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goto out_unlock;
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cpumask_and(&mask, &p->thread.user_cpus_allowed, cpu_possible_mask);
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cpumask_or(&allowed, &p->thread.user_cpus_allowed, &p->cpus_allowed);
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cpumask_and(&mask, &allowed, cpu_active_mask);
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out_unlock:
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read_unlock(&tasklist_lock);
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|
|
|
@ -38,7 +38,7 @@ char *mips_get_machine_name(void)
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return mips_machine_name;
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}
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#ifdef CONFIG_OF
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#ifdef CONFIG_USE_OF
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void __init early_init_dt_add_memory_arch(u64 base, u64 size)
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{
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return add_memory_region(base, size, BOOT_MEM_RAM);
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|
|
|
@ -24,7 +24,7 @@ LEAF(relocate_new_kernel)
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process_entry:
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PTR_L s2, (s0)
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PTR_ADD s0, s0, SZREG
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PTR_ADDIU s0, s0, SZREG
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/*
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* In case of a kdump/crash kernel, the indirection page is not
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|
@ -61,9 +61,9 @@ copy_word:
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/* copy page word by word */
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REG_L s5, (s2)
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REG_S s5, (s4)
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PTR_ADD s4, s4, SZREG
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PTR_ADD s2, s2, SZREG
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LONG_SUB s6, s6, 1
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PTR_ADDIU s4, s4, SZREG
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PTR_ADDIU s2, s2, SZREG
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LONG_ADDIU s6, s6, -1
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beq s6, zero, process_entry
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b copy_word
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b process_entry
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|
|
|
@ -284,7 +284,7 @@ static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
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if (action == 0)
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scheduler_ipi();
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else
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smp_call_function_interrupt();
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generic_smp_call_function_interrupt();
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return IRQ_HANDLED;
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}
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|
@ -336,7 +336,7 @@ static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
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if (action & SMP_RESCHEDULE_YOURSELF)
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scheduler_ipi();
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if (action & SMP_CALL_FUNCTION)
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smp_call_function_interrupt();
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generic_smp_call_function_interrupt();
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|
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return IRQ_HANDLED;
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}
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|
|
|
@ -192,16 +192,6 @@ asmlinkage void start_secondary(void)
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cpu_startup_entry(CPUHP_ONLINE);
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}
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/*
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* Call into both interrupt handlers, as we share the IPI for them
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*/
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void __irq_entry smp_call_function_interrupt(void)
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{
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irq_enter();
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generic_smp_call_function_interrupt();
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irq_exit();
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}
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static void stop_this_cpu(void *dummy)
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{
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/*
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|
|
|
@ -192,6 +192,7 @@ static void show_stacktrace(struct task_struct *task,
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void show_stack(struct task_struct *task, unsigned long *sp)
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{
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struct pt_regs regs;
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mm_segment_t old_fs = get_fs();
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if (sp) {
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regs.regs[29] = (unsigned long)sp;
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regs.regs[31] = 0;
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|
@ -210,7 +211,13 @@ void show_stack(struct task_struct *task, unsigned long *sp)
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prepare_frametrace(®s);
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}
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}
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/*
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* show_stack() deals exclusively with kernel mode, so be sure to access
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* the stack in the kernel (not user) address space.
|
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*/
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set_fs(KERNEL_DS);
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show_stacktrace(task, ®s);
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set_fs(old_fs);
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}
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static void show_code(unsigned int __user *pc)
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|
@ -1519,6 +1526,7 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
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const int field = 2 * sizeof(unsigned long);
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int multi_match = regs->cp0_status & ST0_TS;
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enum ctx_state prev_state;
|
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mm_segment_t old_fs = get_fs();
|
||||
|
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prev_state = exception_enter();
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show_regs(regs);
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|
@ -1540,8 +1548,13 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
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dump_tlb_all();
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}
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|
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if (!user_mode(regs))
|
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set_fs(KERNEL_DS);
|
||||
|
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show_code((unsigned int __user *) regs->cp0_epc);
|
||||
|
||||
set_fs(old_fs);
|
||||
|
||||
/*
|
||||
* Some chips may have other causes of machine check (e.g. SB1
|
||||
* graduation timer)
|
||||
|
|
|
@ -438,7 +438,7 @@ do { \
|
|||
: "memory"); \
|
||||
} while(0)
|
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|
||||
#define StoreDW(addr, value, res) \
|
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#define _StoreDW(addr, value, res) \
|
||||
do { \
|
||||
__asm__ __volatile__ ( \
|
||||
".set\tpush\n\t" \
|
||||
|
|
|
@ -293,7 +293,7 @@ static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
|
|||
|
||||
static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
smp_call_function_interrupt();
|
||||
generic_smp_call_function_interrupt();
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
@ -466,6 +466,7 @@ int get_c0_perfcount_int(void)
|
|||
{
|
||||
return ltq_perfcount_irq;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
|
||||
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
|
|
|
@ -266,8 +266,11 @@ void loongson3_ipi_interrupt(struct pt_regs *regs)
|
|||
if (action & SMP_RESCHEDULE_YOURSELF)
|
||||
scheduler_ipi();
|
||||
|
||||
if (action & SMP_CALL_FUNCTION)
|
||||
smp_call_function_interrupt();
|
||||
if (action & SMP_CALL_FUNCTION) {
|
||||
irq_enter();
|
||||
generic_smp_call_function_interrupt();
|
||||
irq_exit();
|
||||
}
|
||||
|
||||
if (action & SMP_ASK_C0COUNT) {
|
||||
BUG_ON(cpu != 0);
|
||||
|
|
|
@ -160,18 +160,18 @@ static inline void setup_protection_map(void)
|
|||
protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
|
||||
protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
|
||||
protection_map[3] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
|
||||
protection_map[4] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ);
|
||||
protection_map[4] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
|
||||
protection_map[5] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
|
||||
protection_map[6] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ);
|
||||
protection_map[6] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
|
||||
protection_map[7] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
|
||||
|
||||
protection_map[8] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
|
||||
protection_map[9] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
|
||||
protection_map[10] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ);
|
||||
protection_map[11] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE);
|
||||
protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ);
|
||||
protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
|
||||
protection_map[13] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
|
||||
protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE | _PAGE_NO_READ);
|
||||
protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE);
|
||||
protection_map[15] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE);
|
||||
|
||||
} else {
|
||||
|
|
|
@ -133,7 +133,8 @@ static void __kprobes __do_page_fault(struct pt_regs *regs, unsigned long write,
|
|||
#endif
|
||||
goto bad_area;
|
||||
}
|
||||
if (!(vma->vm_flags & VM_READ)) {
|
||||
if (!(vma->vm_flags & VM_READ) &&
|
||||
exception_epc(regs) != address) {
|
||||
#if 0
|
||||
pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] RI violation\n",
|
||||
raw_smp_processor_id(),
|
||||
|
|
|
@ -222,7 +222,7 @@ static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
|
|||
|
||||
static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
smp_call_function_interrupt();
|
||||
generic_smp_call_function_interrupt();
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
|
@ -154,6 +154,7 @@ int get_c0_perfcount_int(void)
|
|||
|
||||
return mips_cpu_perf_irq;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
|
||||
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
|
@ -171,14 +172,17 @@ unsigned int get_c0_compare_int(void)
|
|||
|
||||
static void __init init_rtc(void)
|
||||
{
|
||||
/* stop the clock whilst setting it up */
|
||||
CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL);
|
||||
unsigned char freq, ctrl;
|
||||
|
||||
/* 32KHz time base */
|
||||
CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
|
||||
/* Set 32KHz time base if not already set */
|
||||
freq = CMOS_READ(RTC_FREQ_SELECT);
|
||||
if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ)
|
||||
CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
|
||||
|
||||
/* start the clock */
|
||||
CMOS_WRITE(RTC_24H, RTC_CONTROL);
|
||||
/* Ensure SET bit is clear so RTC can run */
|
||||
ctrl = CMOS_READ(RTC_CONTROL);
|
||||
if (ctrl & RTC_SET)
|
||||
CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL);
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
|
|
|
@ -77,6 +77,7 @@ int get_c0_perfcount_int(void)
|
|||
return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
|
||||
return -1;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
|
||||
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
|
|
|
@ -86,7 +86,7 @@ void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
|
|||
{
|
||||
clear_c0_eimr(irq);
|
||||
ack_c0_eirr(irq);
|
||||
smp_call_function_interrupt();
|
||||
generic_smp_call_function_interrupt();
|
||||
set_c0_eimr(irq);
|
||||
}
|
||||
|
||||
|
|
|
@ -114,7 +114,7 @@ static irqreturn_t paravirt_reched_interrupt(int irq, void *dev_id)
|
|||
|
||||
static irqreturn_t paravirt_function_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
smp_call_function_interrupt();
|
||||
generic_smp_call_function_interrupt();
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
|
|
@ -26,6 +26,7 @@ int get_c0_perfcount_int(void)
|
|||
{
|
||||
return gic_get_c0_perfcount_int();
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
|
||||
|
||||
int get_c0_fdc_int(void)
|
||||
{
|
||||
|
|
|
@ -44,7 +44,7 @@ static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
|
|||
|
||||
static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
smp_call_function_interrupt();
|
||||
generic_smp_call_function_interrupt();
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
|
@ -89,6 +89,7 @@ int get_c0_perfcount_int(void)
|
|||
{
|
||||
return rt_perfcount_irq;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
|
||||
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
|
|
|
@ -107,10 +107,14 @@ static void ip27_do_irq_mask0(void)
|
|||
scheduler_ipi();
|
||||
} else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
|
||||
LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
|
||||
smp_call_function_interrupt();
|
||||
irq_enter();
|
||||
generic_smp_call_function_interrupt();
|
||||
irq_exit();
|
||||
} else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
|
||||
LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
|
||||
smp_call_function_interrupt();
|
||||
irq_enter();
|
||||
generic_smp_call_function_interrupt();
|
||||
irq_exit();
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
|
|
|
@ -29,8 +29,6 @@
|
|||
#include <asm/sibyte/bcm1480_regs.h>
|
||||
#include <asm/sibyte/bcm1480_int.h>
|
||||
|
||||
extern void smp_call_function_interrupt(void);
|
||||
|
||||
/*
|
||||
* These are routines for dealing with the bcm1480 smp capabilities
|
||||
* independent of board/firmware
|
||||
|
@ -184,6 +182,9 @@ void bcm1480_mailbox_interrupt(void)
|
|||
if (action & SMP_RESCHEDULE_YOURSELF)
|
||||
scheduler_ipi();
|
||||
|
||||
if (action & SMP_CALL_FUNCTION)
|
||||
smp_call_function_interrupt();
|
||||
if (action & SMP_CALL_FUNCTION) {
|
||||
irq_enter();
|
||||
generic_smp_call_function_interrupt();
|
||||
irq_exit();
|
||||
}
|
||||
}
|
||||
|
|
|
@ -172,6 +172,9 @@ void sb1250_mailbox_interrupt(void)
|
|||
if (action & SMP_RESCHEDULE_YOURSELF)
|
||||
scheduler_ipi();
|
||||
|
||||
if (action & SMP_CALL_FUNCTION)
|
||||
smp_call_function_interrupt();
|
||||
if (action & SMP_CALL_FUNCTION) {
|
||||
irq_enter();
|
||||
generic_smp_call_function_interrupt();
|
||||
irq_exit();
|
||||
}
|
||||
}
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
#include <asm/clock.h>
|
||||
#include <asm/idle.h>
|
||||
|
||||
#include <asm/mach-loongson/loongson.h>
|
||||
#include <asm/mach-loongson64/loongson.h>
|
||||
|
||||
static uint nowait;
|
||||
|
||||
|
|
|
@ -538,7 +538,7 @@ static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
|
|||
|
||||
static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
smp_call_function_interrupt();
|
||||
generic_smp_call_function_interrupt();
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue
Block a user