forked from luck/tmp_suning_uos_patched
irqchip core changes for v4.8 (second set)
- Add Aspeed VIC driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJXdwfpAAoJEP45WPkGe8ZnhM0P/1Y4A4JU8U8kZHLHCAZgxMAT Bvjqj7liwWH/KohM7WEr0DoYG5v2gxcN0tXLENez03sqO8UnDoG44UPDPeRdUR0y lqrVvg5rCHjoEzg2ilO8lpgfY2BLvF9fYTTrj0g79URpnKijqYDlM9e1cfBw0wh8 bVsIBB9WkZFVpWiGE+aONbfDnUN59hrKz/lSdOo88g97Cgs4kl8Rn75mMTqhMpYg 7ttCu6a3dnKUSDFYcOeFHglNXg7gzTsV+FDAQ2NO7ikVDMP4YLAC9XuLuaIUBMbh 3VO41pmhJ1LGzCFQidtG0vDF/e9Sj+ifmTorh+icEspS56OwsG1XVQeqsrLEnBrX gM7jkq9+4861BJKRIM18g94YxPNlHrkw1JifMw3DlTar7sGUk5SSdHys7+wFtc4t X8dGcgiTzv4zGcCRgFbWv78zEqHnnF3LjYtXC7kOqwiSw5vugkqtLocrze5X5D9+ pnPIcuZN3rRvmZu+uO44asmA3quQc9ohE1JvyAcG2zTdNkj54HGbsGihhdEGhHJx tJoXdAssCjQxky8/uca5fb2lAz5yKfTjRx6hb7iu6wys4LDzF/lXl1JrOLbifw0n l/4w5qSxykDhuVtPJQ919HdFMDN9Zum5UDmhOu5t6/3j7fcNizdG3l0ikbyFRwW2 Mp5Z09BfjKKCYo1l2qeG =09Q0 -----END PGP SIGNATURE----- Merge tag 'irqchip-core-4.8-2' of git://git.infradead.org/users/jcooper/linux into irq/core Pull irqchip core changes for v4.8 (second set) from Jason Cooper: - Add Aspeed VIC driver
This commit is contained in:
Thomas Gleixner
commit
4030103b9b
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@ -0,0 +1,22 @@
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Aspeed Vectored Interrupt Controller
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These bindings are for the Aspeed AST2400 interrupt controller register layout.
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The SoC has an legacy register layout, but this driver does not support that
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mode of operation.
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Required properties:
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- compatible : should be "aspeed,ast2400-vic".
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 1.
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Example:
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vic: interrupt-controller@1e6c0080 {
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compatible = "aspeed,ast2400-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1e6c0080 0x80>;
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};
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@ -70,3 +70,4 @@ obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
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obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
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obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
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obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
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obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
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230
drivers/irqchip/irq-aspeed-vic.c
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230
drivers/irqchip/irq-aspeed-vic.c
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/*
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* Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
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*
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* Driver for Aspeed "new" VIC as found in SoC generation 3 and later
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*
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* Based on irq-vic.c:
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/syscore_ops.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <asm/exception.h>
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#include <asm/irq.h>
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/* These definitions correspond to the "new mapping" of the
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* register set that interleaves "high" and "low". The offsets
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* below are for the "low" register, add 4 to get to the high one
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*/
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#define AVIC_IRQ_STATUS 0x00
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#define AVIC_FIQ_STATUS 0x08
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#define AVIC_RAW_STATUS 0x10
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#define AVIC_INT_SELECT 0x18
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#define AVIC_INT_ENABLE 0x20
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#define AVIC_INT_ENABLE_CLR 0x28
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#define AVIC_INT_TRIGGER 0x30
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#define AVIC_INT_TRIGGER_CLR 0x38
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#define AVIC_INT_SENSE 0x40
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#define AVIC_INT_DUAL_EDGE 0x48
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#define AVIC_INT_EVENT 0x50
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#define AVIC_EDGE_CLR 0x58
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#define AVIC_EDGE_STATUS 0x60
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#define NUM_IRQS 64
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struct aspeed_vic {
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void __iomem *base;
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u32 edge_sources[2];
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struct irq_domain *dom;
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};
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static struct aspeed_vic *system_avic;
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static void vic_init_hw(struct aspeed_vic *vic)
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{
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u32 sense;
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/* Disable all interrupts */
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writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);
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writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);
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/* Make sure no soft trigger is on */
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writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);
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writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);
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/* Set everything to be IRQ */
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writel(0, vic->base + AVIC_INT_SELECT);
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writel(0, vic->base + AVIC_INT_SELECT + 4);
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/* Some interrupts have a programable high/low level trigger
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* (4 GPIO direct inputs), for now we assume this was configured
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* by firmware. We read which ones are edge now.
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*/
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sense = readl(vic->base + AVIC_INT_SENSE);
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vic->edge_sources[0] = ~sense;
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sense = readl(vic->base + AVIC_INT_SENSE + 4);
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vic->edge_sources[1] = ~sense;
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/* Clear edge detection latches */
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writel(0xffffffff, vic->base + AVIC_EDGE_CLR);
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writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);
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}
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static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
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{
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struct aspeed_vic *vic = system_avic;
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u32 stat, irq;
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for (;;) {
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irq = 0;
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stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS);
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if (!stat) {
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stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4);
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irq = 32;
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}
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if (stat == 0)
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break;
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irq += ffs(stat) - 1;
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handle_domain_irq(vic->dom, irq, regs);
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}
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}
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static void avic_ack_irq(struct irq_data *d)
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{
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struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
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unsigned int sidx = d->hwirq >> 5;
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unsigned int sbit = 1u << (d->hwirq & 0x1f);
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/* Clear edge latch for edge interrupts, nop for level */
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if (vic->edge_sources[sidx] & sbit)
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writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
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}
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static void avic_mask_irq(struct irq_data *d)
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{
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struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
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unsigned int sidx = d->hwirq >> 5;
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unsigned int sbit = 1u << (d->hwirq & 0x1f);
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writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
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}
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static void avic_unmask_irq(struct irq_data *d)
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{
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struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
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unsigned int sidx = d->hwirq >> 5;
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unsigned int sbit = 1u << (d->hwirq & 0x1f);
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writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);
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}
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/* For level irq, faster than going through a nop "ack" and mask */
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static void avic_mask_ack_irq(struct irq_data *d)
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{
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struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
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unsigned int sidx = d->hwirq >> 5;
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unsigned int sbit = 1u << (d->hwirq & 0x1f);
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/* First mask */
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writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
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/* Then clear edge latch for edge interrupts */
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if (vic->edge_sources[sidx] & sbit)
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writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
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}
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static struct irq_chip avic_chip = {
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.name = "AVIC",
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.irq_ack = avic_ack_irq,
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.irq_mask = avic_mask_irq,
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.irq_unmask = avic_unmask_irq,
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.irq_mask_ack = avic_mask_ack_irq,
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};
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static int avic_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct aspeed_vic *vic = d->host_data;
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unsigned int sidx = hwirq >> 5;
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unsigned int sbit = 1u << (hwirq & 0x1f);
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/* Check if interrupt exists */
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if (sidx > 1)
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return -EPERM;
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if (vic->edge_sources[sidx] & sbit)
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irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq);
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else
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irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq);
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irq_set_chip_data(irq, vic);
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irq_set_probe(irq);
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return 0;
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}
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static struct irq_domain_ops avic_dom_ops = {
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.map = avic_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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static int __init avic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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void __iomem *regs;
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struct aspeed_vic *vic;
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if (WARN(parent, "non-root Aspeed VIC not supported"))
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return -EINVAL;
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if (WARN(system_avic, "duplicate Aspeed VIC not supported"))
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return -EINVAL;
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regs = of_iomap(node, 0);
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if (WARN_ON(!regs))
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return -EIO;
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vic = kzalloc(sizeof(struct aspeed_vic), GFP_KERNEL);
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if (WARN_ON(!vic)) {
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iounmap(regs);
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return -ENOMEM;
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}
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vic->base = regs;
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/* Initialize soures, all masked */
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vic_init_hw(vic);
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/* Ready to receive interrupts */
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system_avic = vic;
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set_handle_irq(avic_handle_irq);
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/* Register our domain */
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vic->dom = irq_domain_add_simple(node, NUM_IRQS, 0,
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&avic_dom_ops, vic);
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return 0;
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}
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IRQCHIP_DECLARE(aspeed_new_vic, "aspeed,ast2400-vic", avic_of_init);
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