forked from luck/tmp_suning_uos_patched
microblaze_v8: Cpuinfo handling
Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek
parent
8e0ee43bc2
commit
406107dacd
102
arch/microblaze/include/asm/cpuinfo.h
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102
arch/microblaze/include/asm/cpuinfo.h
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@ -0,0 +1,102 @@
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/*
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* Generic support for queying CPU info
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*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2007 John Williams <jwilliams@itee.uq.edu.au>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#ifndef _ASM_MICROBLAZE_CPUINFO_H
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#define _ASM_MICROBLAZE_CPUINFO_H
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#include <asm/prom.h>
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/* CPU Version and FPGA Family code conversion table type */
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struct cpu_ver_key {
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const char *s;
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const unsigned k;
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};
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extern const struct cpu_ver_key cpu_ver_lookup[];
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struct family_string_key {
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const char *s;
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const unsigned k;
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};
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extern const struct family_string_key family_string_lookup[];
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struct cpuinfo {
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/* Core CPU configuration */
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u32 use_instr;
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u32 use_mult;
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u32 use_fpu;
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u32 use_exc;
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u32 ver_code;
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u32 mmu;
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/* CPU caches */
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u32 use_icache;
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u32 icache_tagbits;
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u32 icache_write;
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u32 icache_line;
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u32 icache_size;
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unsigned long icache_base;
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unsigned long icache_high;
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u32 use_dcache;
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u32 dcache_tagbits;
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u32 dcache_write;
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u32 dcache_line;
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u32 dcache_size;
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unsigned long dcache_base;
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unsigned long dcache_high;
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/* Bus connections */
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u32 use_dopb;
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u32 use_iopb;
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u32 use_dlmb;
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u32 use_ilmb;
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u32 num_fsl;
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/* CPU interrupt line info */
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u32 irq_edge;
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u32 irq_positive;
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u32 area_optimised;
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/* HW debug support */
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u32 hw_debug;
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u32 num_pc_brk;
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u32 num_rd_brk;
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u32 num_wr_brk;
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u32 cpu_clock_freq; /* store real freq of cpu */
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u32 freq_div_hz; /* store freq/HZ */
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/* FPGA family */
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u32 fpga_family_code;
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/* User define */
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u32 pvr_user1;
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u32 pvr_user2;
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};
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extern struct cpuinfo cpuinfo;
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/* fwd declarations of the various CPUinfo populators */
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void setup_cpuinfo(void);
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void set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu);
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void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu);
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static inline unsigned int fcpu(struct device_node *cpu, char *n)
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{
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int *val;
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return (val = (int *) of_get_property(cpu, n, NULL)) ? *val : 0;
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}
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#endif /* _ASM_MICROBLAZE_CPUINFO_H */
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101
arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
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101
arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
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@ -0,0 +1,101 @@
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/*
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* Support for MicroBlaze PVR (processor version register)
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*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2007 John Williams <john.williams@petalogix.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/string.h>
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#include <asm/pvr.h>
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#include <asm/cpuinfo.h>
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/*
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* Helper macro to map between fields in our struct cpuinfo, and
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* the PVR macros in pvr.h.
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*/
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#define CI(c, p) { ci->c = PVR_##p(pvr); }
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#define err_printk(x) \
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early_printk("ERROR: Microblaze " x " - different for PVR and DTS\n");
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void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
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{
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struct pvr_s pvr;
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int temp; /* for saving temp value */
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get_pvr(&pvr);
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temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |\
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PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr);
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if (ci->use_instr != temp)
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err_printk("BARREL, MSR, PCMP or DIV");
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ci->use_instr = temp;
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temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr);
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if (ci->use_mult != temp)
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err_printk("HW_MUL");
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ci->use_mult = temp;
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temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr);
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if (ci->use_fpu != temp)
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err_printk("HW_FPU");
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ci->use_fpu = temp;
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ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |\
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PVR_UNALIGNED_EXCEPTION(pvr) |\
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PVR_ILL_OPCODE_EXCEPTION(pvr) |\
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PVR_IOPB_BUS_EXCEPTION(pvr) |\
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PVR_DOPB_BUS_EXCEPTION(pvr) |\
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PVR_DIV_ZERO_EXCEPTION(pvr) |\
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PVR_FPU_EXCEPTION(pvr) |\
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PVR_FSL_EXCEPTION(pvr);
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CI(pvr_user1, USER1);
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CI(pvr_user2, USER2);
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CI(mmu, USE_MMU);
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CI(ver_code, VERSION);
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CI(use_icache, USE_ICACHE);
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CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);
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CI(icache_write, ICACHE_ALLOW_WR);
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CI(icache_line, ICACHE_LINE_LEN);
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CI(icache_size, ICACHE_BYTE_SIZE);
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CI(icache_base, ICACHE_BASEADDR);
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CI(icache_high, ICACHE_HIGHADDR);
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CI(use_dcache, USE_DCACHE);
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CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);
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CI(dcache_write, DCACHE_ALLOW_WR);
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CI(dcache_line, DCACHE_LINE_LEN);
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CI(dcache_size, DCACHE_BYTE_SIZE);
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CI(dcache_base, DCACHE_BASEADDR);
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CI(dcache_high, DCACHE_HIGHADDR);
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CI(use_dopb, D_OPB);
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CI(use_iopb, I_OPB);
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CI(use_dlmb, D_LMB);
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CI(use_ilmb, I_LMB);
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CI(num_fsl, FSL_LINKS);
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CI(irq_edge, INTERRUPT_IS_EDGE);
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CI(irq_positive, EDGE_IS_POSITIVE);
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CI(area_optimised, AREA_OPTIMISED);
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CI(hw_debug, DEBUG_ENABLED);
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CI(num_pc_brk, NUMBER_OF_PC_BRK);
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CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK);
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CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK);
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CI(fpga_family_code, TARGET_FAMILY);
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/* take timebase-frequency from DTS */
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ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency");
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}
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144
arch/microblaze/kernel/cpu/cpuinfo-static.c
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144
arch/microblaze/kernel/cpu/cpuinfo-static.c
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@ -0,0 +1,144 @@
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/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2007 John Williams <john.williams@petalogix.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <asm/cpuinfo.h>
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#include <asm/pvr.h>
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const static char family_string[] = CONFIG_XILINX_MICROBLAZE0_FAMILY;
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const static char cpu_ver_string[] = CONFIG_XILINX_MICROBLAZE0_HW_VER;
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#define err_printk(x) \
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early_printk("ERROR: Microblaze " x "- different for kernel and DTS\n");
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void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
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{
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int i = 0;
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ci->use_instr =
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(fcpu(cpu, "xlnx,use-barrel") ? PVR0_USE_BARREL_MASK : 0) |
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(fcpu(cpu, "xlnx,use-msr-instr") ? PVR2_USE_MSR_INSTR : 0) |
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(fcpu(cpu, "xlnx,use-pcmp-instr") ? PVR2_USE_PCMP_INSTR : 0) |
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(fcpu(cpu, "xlnx,use-div") ? PVR0_USE_DIV_MASK : 0);
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if (CONFIG_XILINX_MICROBLAZE0_USE_BARREL)
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i |= PVR0_USE_BARREL_MASK;
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if (CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR)
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i |= PVR2_USE_MSR_INSTR;
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if (CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR)
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i |= PVR2_USE_PCMP_INSTR;
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if (CONFIG_XILINX_MICROBLAZE0_USE_DIV)
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i |= PVR0_USE_DIV_MASK;
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if (ci->use_instr != i)
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err_printk("BARREL, MSR, PCMP or DIV");
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ci->use_mult = fcpu(cpu, "xlnx,use-hw-mul");
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if (ci->use_mult != CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)
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err_printk("HW_MUL");
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ci->use_mult =
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(ci->use_mult > 1 ?
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(PVR2_USE_MUL64_MASK | PVR0_USE_HW_MUL_MASK) :
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(ci->use_mult == 1 ? PVR0_USE_HW_MUL_MASK : 0));
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ci->use_fpu = fcpu(cpu, "xlnx,use-fpu");
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if (ci->use_fpu != CONFIG_XILINX_MICROBLAZE0_USE_FPU)
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err_printk("HW_FPU");
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ci->use_fpu = (ci->use_fpu > 1 ?
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(PVR2_USE_FPU2_MASK | PVR0_USE_FPU_MASK) :
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(ci->use_fpu == 1 ? PVR0_USE_FPU_MASK : 0));
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ci->use_exc =
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(fcpu(cpu, "xlnx,unaligned-exceptions") ?
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PVR2_UNALIGNED_EXC_MASK : 0) |
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(fcpu(cpu, "xlnx,ill-opcode-exception") ?
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PVR2_ILL_OPCODE_EXC_MASK : 0) |
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(fcpu(cpu, "xlnx,iopb-bus-exception") ?
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PVR2_IOPB_BUS_EXC_MASK : 0) |
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(fcpu(cpu, "xlnx,dopb-bus-exception") ?
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PVR2_DOPB_BUS_EXC_MASK : 0) |
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(fcpu(cpu, "xlnx,div-zero-exception") ?
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PVR2_DIV_ZERO_EXC_MASK : 0) |
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(fcpu(cpu, "xlnx,fpu-exception") ? PVR2_FPU_EXC_MASK : 0) |
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(fcpu(cpu, "xlnx,fsl-exception") ? PVR2_USE_EXTEND_FSL : 0);
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ci->use_icache = fcpu(cpu, "xlnx,use-icache");
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ci->icache_tagbits = fcpu(cpu, "xlnx,addr-tag-bits");
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ci->icache_write = fcpu(cpu, "xlnx,allow-icache-wr");
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ci->icache_line = fcpu(cpu, "xlnx,icache-line-len") << 2;
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if (!ci->icache_line) {
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if (fcpu(cpu, "xlnx,icache-use-fsl"))
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ci->icache_line = 4 << 2;
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else
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ci->icache_line = 1 << 2;
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}
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ci->icache_size = fcpu(cpu, "i-cache-size");
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ci->icache_base = fcpu(cpu, "i-cache-baseaddr");
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ci->icache_high = fcpu(cpu, "i-cache-highaddr");
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ci->use_dcache = fcpu(cpu, "xlnx,use-dcache");
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ci->dcache_tagbits = fcpu(cpu, "xlnx,dcache-addr-tag");
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ci->dcache_write = fcpu(cpu, "xlnx,allow-dcache-wr");
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ci->dcache_line = fcpu(cpu, "xlnx,dcache-line-len") << 2;
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if (!ci->dcache_line) {
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if (fcpu(cpu, "xlnx,dcache-use-fsl"))
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ci->dcache_line = 4 << 2;
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else
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ci->dcache_line = 1 << 2;
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}
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ci->dcache_size = fcpu(cpu, "d-cache-size");
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ci->dcache_base = fcpu(cpu, "d-cache-baseaddr");
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ci->dcache_high = fcpu(cpu, "d-cache-highaddr");
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ci->use_dopb = fcpu(cpu, "xlnx,d-opb");
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ci->use_iopb = fcpu(cpu, "xlnx,i-opb");
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ci->use_dlmb = fcpu(cpu, "xlnx,d-lmb");
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ci->use_ilmb = fcpu(cpu, "xlnx,i-lmb");
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ci->num_fsl = fcpu(cpu, "xlnx,fsl-links");
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ci->irq_edge = fcpu(cpu, "xlnx,interrupt-is-edge");
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ci->irq_positive = fcpu(cpu, "xlnx,edge-is-positive");
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ci->area_optimised = 0;
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ci->hw_debug = fcpu(cpu, "xlnx,debug-enabled");
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ci->num_pc_brk = fcpu(cpu, "xlnx,number-of-pc-brk");
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ci->num_rd_brk = fcpu(cpu, "xlnx,number-of-rd-addr-brk");
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ci->num_wr_brk = fcpu(cpu, "xlnx,number-of-wr-addr-brk");
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ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency");
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ci->pvr_user1 = fcpu(cpu, "xlnx,pvr-user1");
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ci->pvr_user2 = fcpu(cpu, "xlnx,pvr-user2");
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ci->mmu = fcpu(cpu, "xlnx,use-mmu");
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ci->ver_code = 0;
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ci->fpga_family_code = 0;
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/* Do various fixups based on CPU version and FPGA family strings */
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/* Resolved the CPU version code */
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for (i = 0; cpu_ver_lookup[i].s != NULL; i++) {
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if (strcmp(cpu_ver_lookup[i].s, cpu_ver_string) == 0)
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ci->ver_code = cpu_ver_lookup[i].k;
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}
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/* Resolved the fpga family code */
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for (i = 0; family_string_lookup[i].s != NULL; i++) {
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if (strcmp(family_string_lookup[i].s, family_string) == 0)
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ci->fpga_family_code = family_string_lookup[i].k;
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}
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/* FIXME - mb3 and spartan2 do not exist in PVR */
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/* This is mb3 and on a non Spartan2 */
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if (ci->ver_code == 0x20 && ci->fpga_family_code != 0xf0)
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/* Hardware Multiplier in use */
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ci->use_mult = 1;
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}
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86
arch/microblaze/kernel/cpu/cpuinfo.c
Normal file
86
arch/microblaze/kernel/cpu/cpuinfo.c
Normal file
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@ -0,0 +1,86 @@
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/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2007 John Williams <john.williams@petalogix.com>
|
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*
|
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* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file "COPYING" in the main directory of this archive
|
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* for more details.
|
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*/
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <asm/cpuinfo.h>
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#include <asm/pvr.h>
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const struct cpu_ver_key cpu_ver_lookup[] = {
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/* These key value are as per MBV field in PVR0 */
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{"5.00.a", 0x01},
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{"5.00.b", 0x02},
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{"5.00.c", 0x03},
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{"6.00.a", 0x04},
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{"6.00.b", 0x06},
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{"7.00.a", 0x05},
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{"7.00.b", 0x07},
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{"7.10.a", 0x08},
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{"7.10.b", 0x09},
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{"7.10.c", 0x0a},
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{"7.10.d", 0x0b},
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/* FIXME There is no keycode defined in MBV for these versions */
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{"2.10.a", 0x10},
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{"3.00.a", 0x20},
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{"4.00.a", 0x30},
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{"4.00.b", 0x40},
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{NULL, 0},
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};
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/*
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* FIXME Not sure if the actual key is defined by Xilinx in the PVR
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*/
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const struct family_string_key family_string_lookup[] = {
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{"virtex2", 0x4},
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{"virtex2pro", 0x5},
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{"spartan3", 0x6},
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{"virtex4", 0x7},
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{"virtex5", 0x8},
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{"spartan3e", 0x9},
|
||||
{"spartan3a", 0xa},
|
||||
{"spartan3an", 0xb},
|
||||
{"spartan3adsp", 0xc},
|
||||
/* FIXME There is no key code defined for spartan2 */
|
||||
{"spartan2", 0xf0},
|
||||
{NULL, 0},
|
||||
};
|
||||
|
||||
struct cpuinfo cpuinfo;
|
||||
|
||||
void __init setup_cpuinfo(void)
|
||||
{
|
||||
struct device_node *cpu = NULL;
|
||||
|
||||
cpu = (struct device_node *) of_find_node_by_type(NULL, "cpu");
|
||||
if (!cpu)
|
||||
printk(KERN_ERR "You don't have cpu!!!\n");
|
||||
|
||||
printk(KERN_INFO "%s: initialising\n", __func__);
|
||||
|
||||
switch (cpu_has_pvr()) {
|
||||
case 0:
|
||||
printk(KERN_WARNING
|
||||
"%s: No PVR support. Using static CPU info from FDT\n",
|
||||
__func__);
|
||||
set_cpuinfo_static(&cpuinfo, cpu);
|
||||
break;
|
||||
/* FIXME I found weird behavior with MB 7.00.a/b
|
||||
* please do not use FULL PVR with MMU */
|
||||
case 1:
|
||||
printk(KERN_INFO "%s: Using full CPU PVR support\n",
|
||||
__func__);
|
||||
set_cpuinfo_static(&cpuinfo, cpu);
|
||||
set_cpuinfo_pvr_full(&cpuinfo, cpu);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_WARNING "%s: Unsupported PVR setting\n", __func__);
|
||||
set_cpuinfo_static(&cpuinfo, cpu);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user