forked from luck/tmp_suning_uos_patched
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: amd64_edac: Erratum #637 workaround amd64_edac: Factor in CC6 save area amd64_edac: Remove node interleave warning EDAC: Remove debugging output in scrub rate handling
This commit is contained in:
Linus Torvalds
commit
4175242c0d
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@ -211,8 +211,6 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
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scrubval = scrubval & 0x001F;
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amd64_debug("pci-read, sdram scrub control value: %d\n", scrubval);
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for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
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if (scrubrates[i].scrubval == scrubval) {
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retval = scrubrates[i].bandwidth;
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@ -933,25 +931,74 @@ static int k8_early_channel_count(struct amd64_pvt *pvt)
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/* On F10h and later ErrAddr is MC4_ADDR[47:1] */
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static u64 get_error_address(struct mce *m)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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u64 addr;
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u8 start_bit = 1;
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u8 end_bit = 47;
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if (boot_cpu_data.x86 == 0xf) {
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if (c->x86 == 0xf) {
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start_bit = 3;
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end_bit = 39;
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}
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return m->addr & GENMASK(start_bit, end_bit);
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addr = m->addr & GENMASK(start_bit, end_bit);
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/*
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* Erratum 637 workaround
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*/
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if (c->x86 == 0x15) {
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struct amd64_pvt *pvt;
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u64 cc6_base, tmp_addr;
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u32 tmp;
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u8 mce_nid, intlv_en;
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if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7)
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return addr;
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mce_nid = amd_get_nb_id(m->extcpu);
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pvt = mcis[mce_nid]->pvt_info;
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amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
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intlv_en = tmp >> 21 & 0x7;
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/* add [47:27] + 3 trailing bits */
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cc6_base = (tmp & GENMASK(0, 20)) << 3;
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/* reverse and add DramIntlvEn */
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cc6_base |= intlv_en ^ 0x7;
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/* pin at [47:24] */
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cc6_base <<= 24;
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if (!intlv_en)
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return cc6_base | (addr & GENMASK(0, 23));
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amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
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/* faster log2 */
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tmp_addr = (addr & GENMASK(12, 23)) << __fls(intlv_en + 1);
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/* OR DramIntlvSel into bits [14:12] */
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tmp_addr |= (tmp & GENMASK(21, 23)) >> 9;
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/* add remaining [11:0] bits from original MC4_ADDR */
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tmp_addr |= addr & GENMASK(0, 11);
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return cc6_base | tmp_addr;
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}
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return addr;
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}
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static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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int off = range << 3;
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amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo);
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amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
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if (boot_cpu_data.x86 == 0xf)
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if (c->x86 == 0xf)
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return;
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if (!dram_rw(pvt, range))
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@ -959,6 +1006,31 @@ static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
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amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi);
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amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
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/* Factor in CC6 save area by reading dst node's limit reg */
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if (c->x86 == 0x15) {
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struct pci_dev *f1 = NULL;
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u8 nid = dram_dst_node(pvt, range);
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u32 llim;
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f1 = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0x18 + nid, 1));
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if (WARN_ON(!f1))
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return;
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amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
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pvt->ranges[range].lim.lo &= GENMASK(0, 15);
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/* {[39:27],111b} */
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pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
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pvt->ranges[range].lim.hi &= GENMASK(0, 7);
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/* [47:40] */
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pvt->ranges[range].lim.hi |= llim >> 13;
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pci_dev_put(f1);
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}
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}
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static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
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@ -1403,12 +1475,8 @@ static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
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return -EINVAL;
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}
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if (intlv_en &&
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(intlv_sel != ((sys_addr >> 12) & intlv_en))) {
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amd64_warn("Botched intlv bits, en: 0x%x, sel: 0x%x\n",
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intlv_en, intlv_sel);
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if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
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return -EINVAL;
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}
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sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
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@ -196,6 +196,9 @@
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#define DCT_CFG_SEL 0x10C
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#define DRAM_LOCAL_NODE_BASE 0x120
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#define DRAM_LOCAL_NODE_LIM 0x124
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#define DRAM_BASE_HI 0x140
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#define DRAM_LIMIT_HI 0x144
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@ -458,13 +458,13 @@ static ssize_t mci_sdram_scrub_rate_store(struct mem_ctl_info *mci,
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return -EINVAL;
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new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
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if (new_bw >= 0) {
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edac_printk(KERN_DEBUG, EDAC_MC, "Scrub rate set to %d\n", new_bw);
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return count;
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if (new_bw < 0) {
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edac_printk(KERN_WARNING, EDAC_MC,
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"Error setting scrub rate to: %lu\n", bandwidth);
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return -EINVAL;
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}
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edac_printk(KERN_DEBUG, EDAC_MC, "Error setting scrub rate to: %lu\n", bandwidth);
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return -EINVAL;
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return count;
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}
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/*
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@ -483,7 +483,6 @@ static ssize_t mci_sdram_scrub_rate_show(struct mem_ctl_info *mci, char *data)
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return bandwidth;
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}
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edac_printk(KERN_DEBUG, EDAC_MC, "Read scrub rate: %d\n", bandwidth);
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return sprintf(data, "%d\n", bandwidth);
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}
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