forked from luck/tmp_suning_uos_patched
powerpc/85xx: Create dts of each core in CAMP mode for P1020RDB
Create the dts files for each core and splits the devices between the two cores for P1020RDB. Core0 has core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb, eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi. Core1 has l2, eth0, crypto. MPIC is shared between two cores but each core will protect its interrupts from other core by using "protected-sources" of mpic. Fix compatible property for global-util node of P1020si.dtsi. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Prabhakar Kushwaha
Kumar Gala
parent
bc99d09abe
commit
41cd08560b
213
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
Normal file
213
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
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@ -0,0 +1,213 @@
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/*
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* P1020 RDB Core0 Device Tree Source in CAMP mode.
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*
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* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
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* can be shared, all the other devices must be assigned to one core only.
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* This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
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* eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
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*
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* Please note to add "-b 0" for core0's dts compiling.
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "p1020si.dtsi"
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/ {
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model = "fsl,P1020RDB";
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compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
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aliases {
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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serial0 = &serial0;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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cpus {
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PowerPC,P1020@1 {
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status = "disabled";
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};
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};
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memory {
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device_type = "memory";
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};
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localbus@ffe05000 {
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status = "disabled";
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};
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soc@ffe00000 {
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i2c@3000 {
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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serial1: serial@4600 {
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status = "disabled";
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};
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spi@7000 {
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fsl_m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,espi-flash";
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reg = <0>;
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linux,modalias = "fsl_m25p80";
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spi-max-frequency = <40000000>;
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partition@0 {
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/* 512KB for u-boot Bootloader Image */
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reg = <0x0 0x00080000>;
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label = "SPI (RO) U-Boot Image";
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read-only;
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};
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partition@80000 {
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/* 512KB for DTB Image */
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reg = <0x00080000 0x00080000>;
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label = "SPI (RO) DTB Image";
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read-only;
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};
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partition@100000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00100000 0x00400000>;
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label = "SPI (RO) Linux Kernel Image";
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read-only;
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};
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partition@500000 {
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/* 4MB for Compressed RFS Image */
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reg = <0x00500000 0x00400000>;
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label = "SPI (RO) Compressed RFS Image";
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read-only;
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};
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partition@900000 {
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/* 7MB for JFFS2 based RFS */
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reg = <0x00900000 0x00700000>;
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label = "SPI (RW) JFFS2 RFS";
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};
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};
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <3 1>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <0x1>;
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};
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};
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mdio@25000 {
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet0: ethernet@b0000 {
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status = "disabled";
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};
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enet1: ethernet@b1000 {
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phy-handle = <&phy0>;
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tbi-handle = <&tbi0>;
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phy-connection-type = "sgmii";
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};
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enet2: ethernet@b2000 {
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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usb@22000 {
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phy_type = "ulpi";
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};
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/* USB2 is shared with localbus, so it must be disabled
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by default. We can't put 'status = "disabled";' here
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since U-Boot doesn't clear the status property when
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it enables USB2. OTOH, U-Boot does create a new node
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when there isn't any. So, just comment it out.
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usb@23000 {
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phy_type = "ulpi";
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};
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*/
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mpic: pic@40000 {
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protected-sources = <
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42 29 30 34 /* serial1, enet0-queue-group0 */
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17 18 24 45 /* enet0-queue-group1, crypto */
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>;
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};
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};
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pci0: pcie@ffe09000 {
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x4 0x1
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0000 0x0 0x0 0x2 &mpic 0x5 0x1
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0000 0x0 0x0 0x3 &mpic 0x6 0x1
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0000 0x0 0x0 0x4 &mpic 0x7 0x1
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>;
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x0 0x1
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0000 0x0 0x0 0x2 &mpic 0x1 0x1
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0000 0x0 0x0 0x3 &mpic 0x2 0x1
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0000 0x0 0x0 0x4 &mpic 0x3 0x1
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>;
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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148
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
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148
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
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@ -0,0 +1,148 @@
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/*
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* P1020 RDB Core1 Device Tree Source in CAMP mode.
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*
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* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
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* can be shared, all the other devices must be assigned to one core only.
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* This dts allows core1 to have l2, eth0, crypto.
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*
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* Please note to add "-b 1" for core1's dts compiling.
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "p1020si.dtsi"
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/ {
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model = "fsl,P1020RDB";
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compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
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aliases {
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ethernet0 = &enet0;
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serial0 = &serial1;
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};
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cpus {
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PowerPC,P1020@0 {
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status = "disabled";
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};
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};
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memory {
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device_type = "memory";
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};
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localbus@ffe05000 {
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status = "disabled";
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};
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soc@ffe00000 {
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ecm-law@0 {
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status = "disabled";
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};
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ecm@1000 {
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status = "disabled";
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};
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memory-controller@2000 {
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status = "disabled";
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};
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i2c@3000 {
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status = "disabled";
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};
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i2c@3100 {
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status = "disabled";
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};
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serial0: serial@4500 {
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status = "disabled";
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};
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spi@7000 {
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status = "disabled";
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};
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gpio: gpio-controller@f000 {
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status = "disabled";
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};
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dma@21300 {
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status = "disabled";
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};
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mdio@24000 {
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status = "disabled";
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};
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mdio@25000 {
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status = "disabled";
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};
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enet0: ethernet@b0000 {
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fixed-link = <1 1 1000 0 0>;
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phy-connection-type = "rgmii-id";
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};
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enet1: ethernet@b1000 {
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status = "disabled";
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};
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enet2: ethernet@b2000 {
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status = "disabled";
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};
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usb@22000 {
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status = "disabled";
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};
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sdhci@2e000 {
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status = "disabled";
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};
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mpic: pic@40000 {
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protected-sources = <
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16 /* ecm, mem, L2, pci0, pci1 */
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43 42 59 /* i2c, serial0, spi */
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47 63 62 /* gpio, tdm */
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20 21 22 23 /* dma */
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03 02 /* mdio */
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35 36 40 /* enet1-queue-group0 */
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51 52 67 /* enet1-queue-group1 */
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31 32 33 /* enet2-queue-group0 */
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25 26 27 /* enet2-queue-group1 */
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28 72 58 /* usb, sdhci, crypto */
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0xb0 0xb1 0xb2 /* message */
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0xb3 0xb4 0xb5
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0xb6 0xb7
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0xe0 0xe1 0xe2 /* msi */
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0xe3 0xe4 0xe5
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0xe6 0xe7 /* sdhci, crypto , pci */
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>;
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};
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msi@41600 {
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status = "disabled";
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};
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global-utilities@e0000 { //global utilities block
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status = "disabled";
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};
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};
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pci0: pcie@ffe09000 {
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status = "disabled";
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};
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pci1: pcie@ffe0a000 {
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status = "disabled";
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};
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};
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@ -343,7 +343,7 @@ msi@41600 {
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,p1020-guts";
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compatible = "fsl,p1020-guts","fsl,p2020-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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