AcoSail/kernel_optimize_test
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clk: sunxi-ng: sun4i: Export video PLLs

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The video PLLs are used directly by the HDMI controller. Export them so
that we can use them in our DT node.

Signed-off-by: Jonathan Liu <net147@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Jonathan Liu 2017-10-17 20:18:03 +08:00 committed by Maxime Ripard
parent 553c7d5ba2
commit 4328a2186e
2 changed files with 4 additions and 2 deletions
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4
drivers/clk/sunxi-ng/ccu-sun4i-a10.h
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@ -29,7 +29,7 @@
#define CLK_PLL_AUDIO_4X 6
#define CLK_PLL_AUDIO_8X 7
#define CLK_PLL_VIDEO0 8
#define CLK_PLL_VIDEO0_2X 9
/* The PLL_VIDEO0_2X clock is exported */
#define CLK_PLL_VE 10
#define CLK_PLL_DDR_BASE 11
#define CLK_PLL_DDR 12
@ -38,7 +38,7 @@
#define CLK_PLL_PERIPH 15
#define CLK_PLL_PERIPH_SATA 16
#define CLK_PLL_VIDEO1 17
#define CLK_PLL_VIDEO1_2X 18
/* The PLL_VIDEO1_2X clock is exported */
#define CLK_PLL_GPU 19
/* The CPU clock is exported */

2
include/dt-bindings/clock/sun4i-a10-ccu.h
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@ -43,6 +43,8 @@
#define _DT_BINDINGS_CLK_SUN4I_A10_H_
#define CLK_HOSC 1
#define CLK_PLL_VIDEO0_2X 9
#define CLK_PLL_VIDEO1_2X 18
#define CLK_CPU 20
/* AHB Gates */