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ARM: imx: set up pllv3 POWER and BYPASS sequentially

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Currently, POWER and BYPASS bits are set up in a single write to pllv3
register.  This causes problem occasionally from the IPU/HDMI testing.
Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS
sequentially.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo 2013-10-31 09:46:17 +08:00
parent bc3b84da8a
commit 43c9b9e8a4
1 changed files with 10 additions and 2 deletions
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12
arch/arm/mach-imx/clk-pllv3.c
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@ -71,16 +71,24 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 val;
int ret;
val = readl_relaxed(pll->base);
val &= ~BM_PLL_BYPASS;
if (pll->powerup_set)
val |= BM_PLL_POWER;
else
val &= ~BM_PLL_POWER;
writel_relaxed(val, pll->base);
return clk_pllv3_wait_lock(pll);
ret = clk_pllv3_wait_lock(pll);
if (ret)
return ret;
val = readl_relaxed(pll->base);
val &= ~BM_PLL_BYPASS;
writel_relaxed(val, pll->base);
return 0;
}
static void clk_pllv3_unprepare(struct clk_hw *hw)