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sh: Fix up L2 cache probe.

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SH7723 is the first hard silicon to implement the L2, and unsurprisingly,
does the precise inverse of what the specification alleges. XOR the
URAM/L2 size bits to get back in line with the existing parsing logic.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2008-04-09 17:58:22 +09:00
parent e5a4c65bef
commit 440fc172ae
1 changed files with 6 additions and 0 deletions
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6
arch/sh/kernel/cpu/sh4/probe.c
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@ -220,6 +220,12 @@ int __init detect_cpu_and_cache_system(void)
* SH-4A's have an optional PIPT L2. * SH-4A's have an optional PIPT L2.
*/ */
if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) { if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
/* Bug if we can't decode the L2 info */
BUG_ON(!(cvr & 0xf));
/* Silicon and specifications have clearly never met.. */
cvr ^= 0xf;
/* /*
* Size calculation is much more sensible * Size calculation is much more sensible
* than it is for the L1. * than it is for the L1.