forked from luck/tmp_suning_uos_patched
powerpc/qe: QE also shuts down on MPC8568
It appears that QE shuts down on all MPC85xx CPUs (i.e. MPC8568 and MPC8569) and thus needs reset upon resume. So modify qe_alive_during_sleep() to account that. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -154,7 +154,28 @@ int qe_get_snum(void);
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void qe_put_snum(u8 snum);
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unsigned int qe_get_num_of_risc(void);
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unsigned int qe_get_num_of_snums(void);
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int qe_alive_during_sleep(void);
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static inline int qe_alive_during_sleep(void)
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{
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/*
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* MPC8568E reference manual says:
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*
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* "...power down sequence waits for all I/O interfaces to become idle.
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* In some applications this may happen eventually without actively
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* shutting down interfaces, but most likely, software will have to
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* take steps to shut down the eTSEC, QUICC Engine Block, and PCI
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* interfaces before issuing the command (either the write to the core
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* MSR[WE] as described above or writing to POWMGTCSR) to put the
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* device into sleep state."
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*
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* MPC8569E reference manual has a similar paragraph.
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*/
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#ifdef CONFIG_PPC_85xx
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return 0;
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#else
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return 1;
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#endif
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}
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/* we actually use cpm_muram implementation, define this for convenience */
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#define qe_muram_init cpm_muram_init
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@ -65,19 +65,6 @@ static unsigned int qe_num_of_snum;
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static phys_addr_t qebase = -1;
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int qe_alive_during_sleep(void)
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{
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static int ret = -1;
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if (ret != -1)
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return ret;
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ret = !of_find_compatible_node(NULL, NULL, "fsl,mpc8569-pmc");
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return ret;
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}
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EXPORT_SYMBOL(qe_alive_during_sleep);
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phys_addr_t get_qe_base(void)
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{
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struct device_node *qe;
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