forked from luck/tmp_suning_uos_patched
serial: stm32-usart: Add STM32 USART Driver
This drivers adds support to the STM32 USART controller, which is a standard serial driver. Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Peter Hurley <peter@hurleysoftware.com> Reviewed-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Maxime Coquelin
Greg Kroah-Hartman
parent
2a4462418a
commit
48a6092fb4
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@ -1608,6 +1608,23 @@ config SERIAL_SPRD_CONSOLE
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with "earlycon" on the kernel command line. The console is
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enabled when early_param is processed.
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config SERIAL_STM32
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tristate "STMicroelectronics STM32 serial port support"
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select SERIAL_CORE
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depends on ARM || COMPILE_TEST
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help
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This driver is for the on-chip Serial Controller on
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STMicroelectronics STM32 MCUs.
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USART supports Rx & Tx functionality.
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It support all industry standard baud rates.
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If unsure, say N.
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config SERIAL_STM32_CONSOLE
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bool "Support for console on STM32"
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depends on SERIAL_STM32=y
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select SERIAL_CORE_CONSOLE
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endmenu
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config SERIAL_MCTRL_GPIO
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@ -92,6 +92,7 @@ obj-$(CONFIG_SERIAL_FSL_LPUART) += fsl_lpuart.o
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obj-$(CONFIG_SERIAL_CONEXANT_DIGICOLOR) += digicolor-usart.o
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obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o
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obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
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obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
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# GPIOLIB helpers for modem control lines
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obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o
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739
drivers/tty/serial/stm32-usart.c
Normal file
739
drivers/tty/serial/stm32-usart.c
Normal file
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@ -0,0 +1,739 @@
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/*
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* Copyright (C) Maxime Coquelin 2015
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* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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* License terms: GNU General Public License (GPL), version 2
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*
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* Inspired by st-asc.c from STMicroelectronics (c)
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*/
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#if defined(CONFIG_SERIAL_STM32_USART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/module.h>
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#include <linux/serial.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/serial_core.h>
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#include <linux/clk.h>
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#define DRIVER_NAME "stm32-usart"
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/* Register offsets */
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#define USART_SR 0x00
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#define USART_DR 0x04
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#define USART_BRR 0x08
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#define USART_CR1 0x0c
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#define USART_CR2 0x10
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#define USART_CR3 0x14
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#define USART_GTPR 0x18
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/* USART_SR */
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#define USART_SR_PE BIT(0)
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#define USART_SR_FE BIT(1)
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#define USART_SR_NF BIT(2)
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#define USART_SR_ORE BIT(3)
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#define USART_SR_IDLE BIT(4)
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#define USART_SR_RXNE BIT(5)
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#define USART_SR_TC BIT(6)
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#define USART_SR_TXE BIT(7)
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#define USART_SR_LBD BIT(8)
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#define USART_SR_CTS BIT(9)
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#define USART_SR_ERR_MASK (USART_SR_LBD | USART_SR_ORE | \
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USART_SR_FE | USART_SR_PE)
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/* Dummy bits */
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#define USART_SR_DUMMY_RX BIT(16)
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/* USART_DR */
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#define USART_DR_MASK GENMASK(8, 0)
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/* USART_BRR */
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#define USART_BRR_DIV_F_MASK GENMASK(3, 0)
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#define USART_BRR_DIV_M_MASK GENMASK(15, 4)
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#define USART_BRR_DIV_M_SHIFT 4
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/* USART_CR1 */
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#define USART_CR1_SBK BIT(0)
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#define USART_CR1_RWU BIT(1)
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#define USART_CR1_RE BIT(2)
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#define USART_CR1_TE BIT(3)
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#define USART_CR1_IDLEIE BIT(4)
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#define USART_CR1_RXNEIE BIT(5)
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#define USART_CR1_TCIE BIT(6)
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#define USART_CR1_TXEIE BIT(7)
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#define USART_CR1_PEIE BIT(8)
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#define USART_CR1_PS BIT(9)
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#define USART_CR1_PCE BIT(10)
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#define USART_CR1_WAKE BIT(11)
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#define USART_CR1_M BIT(12)
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#define USART_CR1_UE BIT(13)
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#define USART_CR1_OVER8 BIT(15)
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#define USART_CR1_IE_MASK GENMASK(8, 4)
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/* USART_CR2 */
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#define USART_CR2_ADD_MASK GENMASK(3, 0)
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#define USART_CR2_LBDL BIT(5)
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#define USART_CR2_LBDIE BIT(6)
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#define USART_CR2_LBCL BIT(8)
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#define USART_CR2_CPHA BIT(9)
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#define USART_CR2_CPOL BIT(10)
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#define USART_CR2_CLKEN BIT(11)
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#define USART_CR2_STOP_2B BIT(13)
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#define USART_CR2_STOP_MASK GENMASK(13, 12)
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#define USART_CR2_LINEN BIT(14)
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/* USART_CR3 */
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#define USART_CR3_EIE BIT(0)
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#define USART_CR3_IREN BIT(1)
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#define USART_CR3_IRLP BIT(2)
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#define USART_CR3_HDSEL BIT(3)
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#define USART_CR3_NACK BIT(4)
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#define USART_CR3_SCEN BIT(5)
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#define USART_CR3_DMAR BIT(6)
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#define USART_CR3_DMAT BIT(7)
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#define USART_CR3_RTSE BIT(8)
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#define USART_CR3_CTSE BIT(9)
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#define USART_CR3_CTSIE BIT(10)
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#define USART_CR3_ONEBIT BIT(11)
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/* USART_GTPR */
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#define USART_GTPR_PSC_MASK GENMASK(7, 0)
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#define USART_GTPR_GT_MASK GENMASK(15, 8)
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#define DRIVER_NAME "stm32-usart"
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#define STM32_SERIAL_NAME "ttyS"
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#define STM32_MAX_PORTS 6
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struct stm32_port {
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struct uart_port port;
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struct clk *clk;
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bool hw_flow_control;
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};
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static struct stm32_port stm32_ports[STM32_MAX_PORTS];
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static struct uart_driver stm32_usart_driver;
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static void stm32_stop_tx(struct uart_port *port);
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static inline struct stm32_port *to_stm32_port(struct uart_port *port)
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{
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return container_of(port, struct stm32_port, port);
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}
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static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
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{
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u32 val;
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val = readl_relaxed(port->membase + reg);
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val |= bits;
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writel_relaxed(val, port->membase + reg);
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}
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static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
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{
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u32 val;
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val = readl_relaxed(port->membase + reg);
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val &= ~bits;
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writel_relaxed(val, port->membase + reg);
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}
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static void stm32_receive_chars(struct uart_port *port)
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{
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struct tty_port *tport = &port->state->port;
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unsigned long c;
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u32 sr;
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char flag;
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if (port->irq_wake)
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pm_wakeup_event(tport->tty->dev, 0);
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while ((sr = readl_relaxed(port->membase + USART_SR)) & USART_SR_RXNE) {
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sr |= USART_SR_DUMMY_RX;
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c = readl_relaxed(port->membase + USART_DR);
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flag = TTY_NORMAL;
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port->icount.rx++;
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if (sr & USART_SR_ERR_MASK) {
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if (sr & USART_SR_LBD) {
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port->icount.brk++;
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if (uart_handle_break(port))
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continue;
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} else if (sr & USART_SR_ORE) {
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port->icount.overrun++;
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} else if (sr & USART_SR_PE) {
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port->icount.parity++;
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} else if (sr & USART_SR_FE) {
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port->icount.frame++;
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}
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sr &= port->read_status_mask;
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if (sr & USART_SR_LBD)
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flag = TTY_BREAK;
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else if (sr & USART_SR_PE)
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flag = TTY_PARITY;
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else if (sr & USART_SR_FE)
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flag = TTY_FRAME;
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}
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if (uart_handle_sysrq_char(port, c))
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continue;
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uart_insert_char(port, sr, USART_SR_ORE, c, flag);
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}
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spin_unlock(&port->lock);
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tty_flip_buffer_push(tport);
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spin_lock(&port->lock);
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}
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static void stm32_transmit_chars(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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if (port->x_char) {
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writel_relaxed(port->x_char, port->membase + USART_DR);
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port->x_char = 0;
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port->icount.tx++;
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return;
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}
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if (uart_tx_stopped(port)) {
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stm32_stop_tx(port);
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return;
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}
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if (uart_circ_empty(xmit)) {
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stm32_stop_tx(port);
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return;
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}
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writel_relaxed(xmit->buf[xmit->tail], port->membase + USART_DR);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (uart_circ_empty(xmit))
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stm32_stop_tx(port);
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}
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static irqreturn_t stm32_interrupt(int irq, void *ptr)
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{
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struct uart_port *port = ptr;
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u32 sr;
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spin_lock(&port->lock);
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sr = readl_relaxed(port->membase + USART_SR);
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if (sr & USART_SR_RXNE)
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stm32_receive_chars(port);
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if (sr & USART_SR_TXE)
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stm32_transmit_chars(port);
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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}
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static unsigned int stm32_tx_empty(struct uart_port *port)
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{
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return readl_relaxed(port->membase + USART_SR) & USART_SR_TXE;
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}
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static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
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stm32_set_bits(port, USART_CR3, USART_CR3_RTSE);
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else
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stm32_clr_bits(port, USART_CR3, USART_CR3_RTSE);
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}
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static unsigned int stm32_get_mctrl(struct uart_port *port)
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{
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/* This routine is used to get signals of: DCD, DSR, RI, and CTS */
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return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
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}
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/* Transmit stop */
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static void stm32_stop_tx(struct uart_port *port)
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{
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stm32_clr_bits(port, USART_CR1, USART_CR1_TXEIE);
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}
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/* There are probably characters waiting to be transmitted. */
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static void stm32_start_tx(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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if (uart_circ_empty(xmit))
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return;
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stm32_set_bits(port, USART_CR1, USART_CR1_TXEIE | USART_CR1_TE);
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}
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/* Throttle the remote when input buffer is about to overflow. */
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static void stm32_throttle(struct uart_port *port)
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{
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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/* Unthrottle the remote, the input buffer can now accept data. */
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static void stm32_unthrottle(struct uart_port *port)
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{
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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stm32_set_bits(port, USART_CR1, USART_CR1_RXNEIE);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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/* Receive stop */
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static void stm32_stop_rx(struct uart_port *port)
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{
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stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE);
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}
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/* Handle breaks - ignored by us */
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static void stm32_break_ctl(struct uart_port *port, int break_state)
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{
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}
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static int stm32_startup(struct uart_port *port)
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{
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const char *name = to_platform_device(port->dev)->name;
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u32 val;
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int ret;
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ret = request_irq(port->irq, stm32_interrupt, IRQF_NO_SUSPEND,
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name, port);
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if (ret)
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return ret;
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val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
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stm32_set_bits(port, USART_CR1, val);
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return 0;
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}
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static void stm32_shutdown(struct uart_port *port)
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{
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u32 val;
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val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
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stm32_set_bits(port, USART_CR1, val);
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free_irq(port->irq, port);
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}
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static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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unsigned int baud;
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u32 usartdiv, mantissa, fraction, oversampling;
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tcflag_t cflag = termios->c_cflag;
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u32 cr1, cr2, cr3;
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unsigned long flags;
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if (!stm32_port->hw_flow_control)
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cflag &= ~CRTSCTS;
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baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
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spin_lock_irqsave(&port->lock, flags);
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/* Stop serial port and reset value */
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writel_relaxed(0, port->membase + USART_CR1);
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cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE | USART_CR1_RXNEIE;
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cr2 = 0;
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cr3 = 0;
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if (cflag & CSTOPB)
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cr2 |= USART_CR2_STOP_2B;
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if (cflag & PARENB) {
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cr1 |= USART_CR1_PCE;
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if ((cflag & CSIZE) == CS8)
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cr1 |= USART_CR1_M;
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}
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if (cflag & PARODD)
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cr1 |= USART_CR1_PS;
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port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
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if (cflag & CRTSCTS) {
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port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
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cr3 |= USART_CR3_CTSE;
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}
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usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
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/*
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* The USART supports 16 or 8 times oversampling.
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* By default we prefer 16 times oversampling, so that the receiver
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* has a better tolerance to clock deviations.
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* 8 times oversampling is only used to achieve higher speeds.
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*/
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if (usartdiv < 16) {
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oversampling = 8;
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stm32_set_bits(port, USART_CR1, USART_CR1_OVER8);
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} else {
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oversampling = 16;
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stm32_clr_bits(port, USART_CR1, USART_CR1_OVER8);
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}
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mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
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fraction = usartdiv % oversampling;
|
||||
writel_relaxed(mantissa | fraction, port->membase + USART_BRR);
|
||||
|
||||
uart_update_timeout(port, cflag, baud);
|
||||
|
||||
port->read_status_mask = USART_SR_ORE;
|
||||
if (termios->c_iflag & INPCK)
|
||||
port->read_status_mask |= USART_SR_PE | USART_SR_FE;
|
||||
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
|
||||
port->read_status_mask |= USART_SR_LBD;
|
||||
|
||||
/* Characters to ignore */
|
||||
port->ignore_status_mask = 0;
|
||||
if (termios->c_iflag & IGNPAR)
|
||||
port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
|
||||
if (termios->c_iflag & IGNBRK) {
|
||||
port->ignore_status_mask |= USART_SR_LBD;
|
||||
/*
|
||||
* If we're ignoring parity and break indicators,
|
||||
* ignore overruns too (for real raw support).
|
||||
*/
|
||||
if (termios->c_iflag & IGNPAR)
|
||||
port->ignore_status_mask |= USART_SR_ORE;
|
||||
}
|
||||
|
||||
/* Ignore all characters if CREAD is not set */
|
||||
if ((termios->c_cflag & CREAD) == 0)
|
||||
port->ignore_status_mask |= USART_SR_DUMMY_RX;
|
||||
|
||||
writel_relaxed(cr3, port->membase + USART_CR3);
|
||||
writel_relaxed(cr2, port->membase + USART_CR2);
|
||||
writel_relaxed(cr1, port->membase + USART_CR1);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
static const char *stm32_type(struct uart_port *port)
|
||||
{
|
||||
return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
|
||||
}
|
||||
|
||||
static void stm32_release_port(struct uart_port *port)
|
||||
{
|
||||
}
|
||||
|
||||
static int stm32_request_port(struct uart_port *port)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stm32_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
if (flags & UART_CONFIG_TYPE)
|
||||
port->type = PORT_STM32;
|
||||
}
|
||||
|
||||
static int
|
||||
stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
|
||||
{
|
||||
/* No user changeable parameters */
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void stm32_pm(struct uart_port *port, unsigned int state,
|
||||
unsigned int oldstate)
|
||||
{
|
||||
struct stm32_port *stm32port = container_of(port,
|
||||
struct stm32_port, port);
|
||||
unsigned long flags = 0;
|
||||
|
||||
switch (state) {
|
||||
case UART_PM_STATE_ON:
|
||||
clk_prepare_enable(stm32port->clk);
|
||||
break;
|
||||
case UART_PM_STATE_OFF:
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
stm32_clr_bits(port, USART_CR1, USART_CR1_UE);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
clk_disable_unprepare(stm32port->clk);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct uart_ops stm32_uart_ops = {
|
||||
.tx_empty = stm32_tx_empty,
|
||||
.set_mctrl = stm32_set_mctrl,
|
||||
.get_mctrl = stm32_get_mctrl,
|
||||
.stop_tx = stm32_stop_tx,
|
||||
.start_tx = stm32_start_tx,
|
||||
.throttle = stm32_throttle,
|
||||
.unthrottle = stm32_unthrottle,
|
||||
.stop_rx = stm32_stop_rx,
|
||||
.break_ctl = stm32_break_ctl,
|
||||
.startup = stm32_startup,
|
||||
.shutdown = stm32_shutdown,
|
||||
.set_termios = stm32_set_termios,
|
||||
.pm = stm32_pm,
|
||||
.type = stm32_type,
|
||||
.release_port = stm32_release_port,
|
||||
.request_port = stm32_request_port,
|
||||
.config_port = stm32_config_port,
|
||||
.verify_port = stm32_verify_port,
|
||||
};
|
||||
|
||||
static int stm32_init_port(struct stm32_port *stm32port,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct uart_port *port = &stm32port->port;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
port->iotype = UPIO_MEM;
|
||||
port->flags = UPF_BOOT_AUTOCONF;
|
||||
port->ops = &stm32_uart_ops;
|
||||
port->dev = &pdev->dev;
|
||||
port->irq = platform_get_irq(pdev, 0);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
port->membase = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(port->membase))
|
||||
return PTR_ERR(port->membase);
|
||||
port->mapbase = res->start;
|
||||
|
||||
spin_lock_init(&port->lock);
|
||||
|
||||
stm32port->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(stm32port->clk))
|
||||
return PTR_ERR(stm32port->clk);
|
||||
|
||||
/* Ensure that clk rate is correct by enabling the clk */
|
||||
ret = clk_prepare_enable(stm32port->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
stm32port->port.uartclk = clk_get_rate(stm32port->clk);
|
||||
if (!stm32port->port.uartclk)
|
||||
ret = -EINVAL;
|
||||
|
||||
clk_disable_unprepare(stm32port->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
int id;
|
||||
|
||||
if (!np)
|
||||
return NULL;
|
||||
|
||||
id = of_alias_get_id(np, "serial");
|
||||
if (id < 0)
|
||||
id = 0;
|
||||
|
||||
if (WARN_ON(id >= STM32_MAX_PORTS))
|
||||
return NULL;
|
||||
|
||||
stm32_ports[id].hw_flow_control = of_property_read_bool(np,
|
||||
"auto-flow-control");
|
||||
stm32_ports[id].port.line = id;
|
||||
return &stm32_ports[id];
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id stm32_match[] = {
|
||||
{ .compatible = "st,stm32-usart", },
|
||||
{ .compatible = "st,stm32-uart", },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, stm32_match);
|
||||
#endif
|
||||
|
||||
static int stm32_serial_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct stm32_port *stm32port;
|
||||
|
||||
stm32port = stm32_of_get_stm32_port(pdev);
|
||||
if (!stm32port)
|
||||
return -ENODEV;
|
||||
|
||||
ret = stm32_init_port(stm32port, pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, &stm32port->port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_serial_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct uart_port *port = platform_get_drvdata(pdev);
|
||||
|
||||
return uart_remove_one_port(&stm32_usart_driver, port);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_SERIAL_STM32_CONSOLE
|
||||
static void stm32_console_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
while (!(readl_relaxed(port->membase + USART_SR) & USART_SR_TXE))
|
||||
cpu_relax();
|
||||
|
||||
writel_relaxed(ch, port->membase + USART_DR);
|
||||
}
|
||||
|
||||
static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
|
||||
{
|
||||
struct uart_port *port = &stm32_ports[co->index].port;
|
||||
unsigned long flags;
|
||||
u32 old_cr1, new_cr1;
|
||||
int locked = 1;
|
||||
|
||||
local_irq_save(flags);
|
||||
if (port->sysrq)
|
||||
locked = 0;
|
||||
else if (oops_in_progress)
|
||||
locked = spin_trylock(&port->lock);
|
||||
else
|
||||
spin_lock(&port->lock);
|
||||
|
||||
/* Save and disable interrupts */
|
||||
old_cr1 = readl_relaxed(port->membase + USART_CR1);
|
||||
new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
|
||||
writel_relaxed(new_cr1, port->membase + USART_CR1);
|
||||
|
||||
uart_console_write(port, s, cnt, stm32_console_putchar);
|
||||
|
||||
/* Restore interrupt state */
|
||||
writel_relaxed(old_cr1, port->membase + USART_CR1);
|
||||
|
||||
if (locked)
|
||||
spin_unlock(&port->lock);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static int stm32_console_setup(struct console *co, char *options)
|
||||
{
|
||||
struct stm32_port *stm32port;
|
||||
int baud = 9600;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
int flow = 'n';
|
||||
|
||||
if (co->index >= STM32_MAX_PORTS)
|
||||
return -ENODEV;
|
||||
|
||||
stm32port = &stm32_ports[co->index];
|
||||
|
||||
/*
|
||||
* This driver does not support early console initialization
|
||||
* (use ARM early printk support instead), so we only expect
|
||||
* this to be called during the uart port registration when the
|
||||
* driver gets probed and the port should be mapped at that point.
|
||||
*/
|
||||
if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
|
||||
return -ENXIO;
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
|
||||
return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct console stm32_console = {
|
||||
.name = STM32_SERIAL_NAME,
|
||||
.device = uart_console_device,
|
||||
.write = stm32_console_write,
|
||||
.setup = stm32_console_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &stm32_usart_driver,
|
||||
};
|
||||
|
||||
#define STM32_SERIAL_CONSOLE (&stm32_console)
|
||||
|
||||
#else
|
||||
#define STM32_SERIAL_CONSOLE NULL
|
||||
#endif /* CONFIG_SERIAL_STM32_CONSOLE */
|
||||
|
||||
static struct uart_driver stm32_usart_driver = {
|
||||
.driver_name = DRIVER_NAME,
|
||||
.dev_name = STM32_SERIAL_NAME,
|
||||
.major = 0,
|
||||
.minor = 0,
|
||||
.nr = STM32_MAX_PORTS,
|
||||
.cons = STM32_SERIAL_CONSOLE,
|
||||
};
|
||||
|
||||
static struct platform_driver stm32_serial_driver = {
|
||||
.probe = stm32_serial_probe,
|
||||
.remove = stm32_serial_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = of_match_ptr(stm32_match),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init usart_init(void)
|
||||
{
|
||||
static char banner[] __initdata = "STM32 USART driver initialized";
|
||||
int ret;
|
||||
|
||||
pr_info("%s\n", banner);
|
||||
|
||||
ret = uart_register_driver(&stm32_usart_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = platform_driver_register(&stm32_serial_driver);
|
||||
if (ret)
|
||||
uart_unregister_driver(&stm32_usart_driver);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit usart_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&stm32_serial_driver);
|
||||
uart_unregister_driver(&stm32_usart_driver);
|
||||
}
|
||||
|
||||
module_init(usart_init);
|
||||
module_exit(usart_exit);
|
||||
|
||||
MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -258,4 +258,7 @@
|
|||
/* Cris v10 / v32 SoC */
|
||||
#define PORT_CRIS 112
|
||||
|
||||
/* STM32 USART */
|
||||
#define PORT_STM32 113
|
||||
|
||||
#endif /* _UAPILINUX_SERIAL_CORE_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user