forked from luck/tmp_suning_uos_patched
watchdog: octeon-wdt: Remove old boot vector code.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17209/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Steven J. Hill
Ralf Baechle
parent
9438a86a07
commit
49d148b4e5
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@ -73,6 +73,7 @@
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#include <asm/uasm.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-boot-vector.h>
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/* The count needed to achieve timeout_sec. */
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static unsigned int timeout_cnt;
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@ -104,122 +105,10 @@ MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static u32 nmi_stage1_insns[64] __initdata;
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/* We need one branch and therefore one relocation per target label. */
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static struct uasm_label labels[5] __initdata;
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static struct uasm_reloc relocs[5] __initdata;
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enum lable_id {
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label_enter_bootloader = 1
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};
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/* Some CP0 registers */
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#define K0 26
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#define C0_CVMMEMCTL 11, 7
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#define C0_STATUS 12, 0
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#define C0_EBASE 15, 1
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#define C0_DESAVE 31, 0
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static struct cvmx_boot_vector_element *octeon_wdt_bootvector;
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void octeon_wdt_nmi_stage2(void);
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static void __init octeon_wdt_build_stage1(void)
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{
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int i;
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int len;
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u32 *p = nmi_stage1_insns;
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#ifdef CONFIG_HOTPLUG_CPU
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struct uasm_label *l = labels;
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struct uasm_reloc *r = relocs;
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#endif
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/*
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* For the next few instructions running the debugger may
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* cause corruption of k0 in the saved registers. Since we're
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* about to crash, nobody probably cares.
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*
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* Save K0 into the debug scratch register
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*/
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uasm_i_dmtc0(&p, K0, C0_DESAVE);
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uasm_i_mfc0(&p, K0, C0_STATUS);
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#ifdef CONFIG_HOTPLUG_CPU
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if (octeon_bootloader_entry_addr)
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uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI),
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label_enter_bootloader);
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#endif
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/* Force 64-bit addressing enabled */
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uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX);
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uasm_i_mtc0(&p, K0, C0_STATUS);
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#ifdef CONFIG_HOTPLUG_CPU
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if (octeon_bootloader_entry_addr) {
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uasm_i_mfc0(&p, K0, C0_EBASE);
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/* Coreid number in K0 */
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uasm_i_andi(&p, K0, K0, 0xf);
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/* 8 * coreid in bits 16-31 */
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uasm_i_dsll_safe(&p, K0, K0, 3 + 16);
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uasm_i_ori(&p, K0, K0, 0x8001);
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uasm_i_dsll_safe(&p, K0, K0, 16);
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uasm_i_ori(&p, K0, K0, 0x0700);
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uasm_i_drotr_safe(&p, K0, K0, 32);
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/*
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* Should result in: 0x8001,0700,0000,8*coreid which is
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* CVMX_CIU_WDOGX(coreid) - 0x0500
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*
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* Now ld K0, CVMX_CIU_WDOGX(coreid)
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*/
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uasm_i_ld(&p, K0, 0x500, K0);
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/*
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* If bit one set handle the NMI as a watchdog event.
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* otherwise transfer control to bootloader.
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*/
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uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);
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uasm_i_nop(&p);
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}
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#endif
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/* Clear Dcache so cvmseg works right. */
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uasm_i_cache(&p, 1, 0, 0);
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/* Use K0 to do a read/modify/write of CVMMEMCTL */
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uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL);
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/* Clear out the size of CVMSEG */
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uasm_i_dins(&p, K0, 0, 0, 6);
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/* Set CVMSEG to its largest value */
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uasm_i_ori(&p, K0, K0, 0x1c0 | 54);
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/* Store the CVMMEMCTL value */
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uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL);
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/* Load the address of the second stage handler */
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UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2);
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uasm_i_jr(&p, K0);
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uasm_i_dmfc0(&p, K0, C0_DESAVE);
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#ifdef CONFIG_HOTPLUG_CPU
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if (octeon_bootloader_entry_addr) {
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uasm_build_label(&l, p, label_enter_bootloader);
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/* Jump to the bootloader and restore K0 */
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UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);
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uasm_i_jr(&p, K0);
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uasm_i_dmfc0(&p, K0, C0_DESAVE);
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}
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#endif
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uasm_resolve_relocs(relocs, labels);
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len = (int)(p - nmi_stage1_insns);
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pr_debug("Synthesized NMI stage 1 handler (%d instructions)\n", len);
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pr_debug("\t.set push\n");
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pr_debug("\t.set noreorder\n");
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for (i = 0; i < len; i++)
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pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]);
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pr_debug("\t.set pop\n");
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if (len > 32)
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panic("NMI stage 1 handler exceeds 32 instructions, was %d\n",
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len);
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}
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static int cpu2core(int cpu)
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{
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#ifdef CONFIG_SMP
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@ -402,6 +291,8 @@ static int octeon_wdt_cpu_online(unsigned int cpu)
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core = cpu2core(cpu);
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octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2;
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/* Disable it before doing anything with the interrupts. */
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ciu_wdog.u64 = 0;
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cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
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@ -544,6 +435,12 @@ static int __init octeon_wdt_init(void)
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int ret;
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u64 *ptr;
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octeon_wdt_bootvector = cvmx_boot_vector_get();
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if (!octeon_wdt_bootvector) {
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pr_err("Error: Cannot allocate boot vector.\n");
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return -ENOMEM;
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}
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/*
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* Watchdog time expiration length = The 16 bits of LEN
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* represent the most significant bits of a 24 bit decrementer
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@ -576,17 +473,6 @@ static int __init octeon_wdt_init(void)
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return ret;
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}
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/* Build the NMI handler ... */
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octeon_wdt_build_stage1();
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/* ... and install it. */
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ptr = (u64 *) nmi_stage1_insns;
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for (i = 0; i < 16; i++) {
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]);
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}
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
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cpumask_clear(&irq_enabled_cpus);
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online",
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@ -3,20 +3,40 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 Cavium Networks
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* Copyright (C) 2007-2017 Cavium, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#define SAVE_REG(r) sd $r, -32768+6912-(32-r)*8($0)
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#define CVMSEG_BASE -32768
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#define CVMSEG_SIZE 6912
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#define SAVE_REG(r) sd $r, CVMSEG_BASE + CVMSEG_SIZE - ((32 - r) * 8)($0)
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NESTED(octeon_wdt_nmi_stage2, 0, sp)
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.set push
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.set noreorder
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.set noat
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/* Save all registers to the top CVMSEG. This shouldn't
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/* Clear Dcache so cvmseg works right. */
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cache 1,0($0)
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/* Use K0 to do a read/modify/write of CVMMEMCTL */
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dmfc0 k0, $11, 7
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/* Clear out the size of CVMSEG */
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dins k0, $0, 0, 6
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/* Set CVMSEG to its largest value */
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ori k0, k0, 0x1c0 | 54
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/* Store the CVMMEMCTL value */
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dmtc0 k0, $11, 7
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/*
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* Restore K0 from the debug scratch register, it was saved in
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* the boot-vector code.
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*/
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dmfc0 k0, $31
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/*
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* Save all registers to the top CVMSEG. This shouldn't
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* corrupt any state used by the kernel. Also all registers
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* should have the value right before the NMI. */
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* should have the value right before the NMI.
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*/
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SAVE_REG(0)
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SAVE_REG(1)
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SAVE_REG(2)
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@ -49,16 +69,22 @@
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SAVE_REG(29)
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SAVE_REG(30)
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SAVE_REG(31)
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/* Write zero to all CVMSEG locations per Core-15169 */
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dli a0, CVMSEG_SIZE - (33 * 8)
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1: sd zero, CVMSEG_BASE(a0)
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daddiu a0, a0, -8
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bgez a0, 1b
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nop
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/* Set the stack to begin right below the registers */
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li sp, -32768+6912-32*8
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dli sp, CVMSEG_BASE + CVMSEG_SIZE - (32 * 8)
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/* Load the address of the third stage handler */
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dla a0, octeon_wdt_nmi_stage3
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dla $25, octeon_wdt_nmi_stage3
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/* Call the third stage handler */
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jal a0
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jal $25
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/* a0 is the address of the saved registers */
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move a0, sp
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/* Loop forvever if we get here. */
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1: b 1b
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2: b 2b
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nop
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.set pop
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END(octeon_wdt_nmi_stage2)
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