forked from luck/tmp_suning_uos_patched
pwm: samsung: Fix output race on disabling
When disabling the Samsung PWM the output state remains at the level it was at the end of a PWM cycle. In other words, calling pwm_disable() when at 100% duty cycle will keep the output active, while at all other settings the output will go/stay inactive. On top of that the Samsung PWM settings are double-buffered, which means the new settings only get applied at the start of a new PWM cycle. This results in a race if the PWM is at 100% duty cycle and a driver calls: pwm_config(pwm, 0, period); pwm_disable(pwm); In this case the PWMs output will unexpectedly stay active, unless a new PWM cycle happened to start between the register writes in pwm_config() and pwm_disable(). As far as I can tell this is a regression introduced by3bdf878
, before that a call to pwm_config() would call pwm_samsung_enable() which, while heavy-handed, made sure the expected settings were live. To resolve this, while not re-introducing the issues3bdf878
(flickering as the PWM got reset while in a PWM cycle) fixed, only force an update of the settings when at 100% duty cycle, which shouldn't have any noticeable effect on the output but is enough to ensure the behaviour is as expected on disable. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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@ -269,12 +269,31 @@ static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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spin_unlock_irqrestore(&samsung_pwm_lock, flags);
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}
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static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
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struct pwm_device *pwm)
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{
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unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
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u32 tcon;
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unsigned long flags;
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spin_lock_irqsave(&samsung_pwm_lock, flags);
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tcon = readl(chip->base + REG_TCON);
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tcon |= TCON_MANUALUPDATE(tcon_chan);
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writel(tcon, chip->base + REG_TCON);
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tcon &= ~TCON_MANUALUPDATE(tcon_chan);
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writel(tcon, chip->base + REG_TCON);
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spin_unlock_irqrestore(&samsung_pwm_lock, flags);
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}
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static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
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struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
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u32 tin_ns = chan->tin_ns, tcnt, tcmp;
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u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
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/*
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* We currently avoid using 64bit arithmetic by using the
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@ -288,6 +307,7 @@ static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
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return 0;
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tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
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oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
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/* We need tick count for calculation, not last tick. */
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++tcnt;
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@ -335,6 +355,16 @@ static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
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writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
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writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
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/*
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* In case the PWM is currently at 100% duty cycle, force a manual
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* update to prevent the signal staying high if the PWM is disabled
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* shortly afer this update (before it autoreloaded the new values).
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*/
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if (oldtcmp == (u32) -1) {
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dev_dbg(our_chip->chip.dev, "Forcing manual update");
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pwm_samsung_manual_update(our_chip, pwm);
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}
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chan->period_ns = period_ns;
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chan->tin_ns = tin_ns;
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chan->duty_ns = duty_ns;
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