AcoSail/kernel_optimize_test
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Rename .data.cacheline_aligned to .data..cacheline_aligned.

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Signed-off-by: Tim Abbott <tabbott@ksplice.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Denys Vlasenko <vda.linux@googlemail.com>
Signed-off-by: Michal Marek <mmarek@suse.cz>
This commit is contained in:
Tim Abbott 2010-02-20 01:03:34 +01:00 committed by Michal Marek
parent bc75cc6b56
commit 4af57b787b
4 changed files with 4 additions and 4 deletions
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2
arch/powerpc/kernel/vmlinux.lds.S
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@ -231,7 +231,7 @@ SECTIONS
PAGE_ALIGNED_DATA(PAGE_SIZE)
}
.data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET) {
.data..cacheline_aligned : AT(ADDR(.data..cacheline_aligned) - LOAD_OFFSET) {
CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
}

2
arch/x86/kernel/init_task.c
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@ -34,7 +34,7 @@ EXPORT_SYMBOL(init_task);
/*
* per-CPU TSS segments. Threads are completely 'soft' on Linux,
* no more per-task TSS's. The TSS size is kept cacheline-aligned
* so they are allowed to end up in the .data.cacheline_aligned
* so they are allowed to end up in the .data..cacheline_aligned
* section. Since TSS's are completely CPU-local, we want them
* on exact cacheline boundaries, to eliminate cacheline ping-pong.
*/

2
include/asm-generic/vmlinux.lds.h
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@ -189,7 +189,7 @@
#define CACHELINE_ALIGNED_DATA(align) \
. = ALIGN(align); \
*(.data.cacheline_aligned)
*(.data..cacheline_aligned)
#define INIT_TASK_DATA(align) \
. = ALIGN(align); \

2
include/linux/cache.h
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@ -31,7 +31,7 @@
#ifndef __cacheline_aligned
#define __cacheline_aligned \
__attribute__((__aligned__(SMP_CACHE_BYTES), \
__section__(".data.cacheline_aligned")))
__section__(".data..cacheline_aligned")))
#endif /* __cacheline_aligned */
#ifndef __cacheline_aligned_in_smp