forked from luck/tmp_suning_uos_patched
ARM: shmobile: Add r8a7791 legacy SDHI clocks
Add legacy r8a7791 SDHI clocks. This to allow the SDHI devices to be used by legacy Koelsch board support. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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b998da0541
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@ -61,6 +61,7 @@
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#define MSTPSR1 IOMEM(0xe6150038)
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#define MSTPSR1 IOMEM(0xe6150038)
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#define MSTPSR2 IOMEM(0xe6150040)
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#define MSTPSR2 IOMEM(0xe6150040)
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#define MSTPSR3 IOMEM(0xe6150048)
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#define MSTPSR5 IOMEM(0xe615003c)
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#define MSTPSR5 IOMEM(0xe615003c)
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#define MSTPSR7 IOMEM(0xe61501c4)
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#define MSTPSR7 IOMEM(0xe61501c4)
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#define MSTPSR8 IOMEM(0xe61509a0)
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#define MSTPSR8 IOMEM(0xe61509a0)
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@ -69,8 +70,8 @@
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#define MODEMR 0xE6160060
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#define MODEMR 0xE6160060
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#define SDCKCR 0xE6150074
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#define SDCKCR 0xE6150074
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#define SD2CKCR 0xE6150078
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#define SD1CKCR 0xE6150078
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#define SD3CKCR 0xE615007C
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#define SD2CKCR 0xE615026c
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#define MMC0CKCR 0xE6150240
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#define MMC0CKCR 0xE6150240
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#define MMC1CKCR 0xE6150244
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#define MMC1CKCR 0xE6150244
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#define SSPCKCR 0xE6150248
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#define SSPCKCR 0xE6150248
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@ -134,6 +135,39 @@ static struct clk *main_clks[] = {
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&zs_clk,
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&zs_clk,
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};
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};
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/* SDHI (DIV4) clock */
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum {
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DIV4_SDH, DIV4_SD0,
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DIV4_NR
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};
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static struct clk div4_clks[DIV4_NR] = {
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[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
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[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
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};
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/* DIV6 clocks */
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enum {
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DIV6_SD1, DIV6_SD2,
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DIV6_NR
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};
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_SD1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
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[DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
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};
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/* MSTP */
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/* MSTP */
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enum {
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enum {
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MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
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MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
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@ -144,6 +178,7 @@ enum {
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MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
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MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
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MSTP719, MSTP718, MSTP715, MSTP714,
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MSTP719, MSTP718, MSTP715, MSTP714,
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MSTP522,
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MSTP522,
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MSTP314, MSTP312, MSTP311,
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MSTP216, MSTP207, MSTP206,
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MSTP216, MSTP207, MSTP206,
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MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
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MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
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MSTP124,
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MSTP124,
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@ -174,6 +209,9 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
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[MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
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[MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
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[MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
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[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
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[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
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[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
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[MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
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[MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */
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[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
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[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
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[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
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[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
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[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
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[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
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@ -224,6 +262,9 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
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CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
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CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
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CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
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CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
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CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
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CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
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CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
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CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
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CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
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CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
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@ -285,6 +326,12 @@ void __init r8a7791_clock_init(void)
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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if (!ret)
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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