forked from luck/tmp_suning_uos_patched
arm64: Add hwcaps for crypto and CRC32 extensions.
Advertise the optional cryptographic and CRC32 instructions to user space where present. Several hwcap bits [3-7] are allocated. Signed-off-by: Steve Capper <steve.capper@linaro.org> [bit 2 is taken now so use bits 3-7 instead] Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -22,6 +22,10 @@
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#define HWCAP_FP (1 << 0)
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#define HWCAP_ASIMD (1 << 1)
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#define HWCAP_EVTSTRM (1 << 2)
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#define HWCAP_AES (1 << 3)
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#define HWCAP_PMULL (1 << 4)
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#define HWCAP_SHA1 (1 << 5)
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#define HWCAP_SHA2 (1 << 6)
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#define HWCAP_CRC32 (1 << 7)
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#endif /* _UAPI__ASM_HWCAP_H */
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@ -126,6 +126,7 @@ bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
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static void __init setup_processor(void)
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{
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struct cpu_info *cpu_info;
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u64 features, block;
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cpu_info = lookup_processor_type(read_cpuid_id());
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if (!cpu_info) {
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@ -141,6 +142,37 @@ static void __init setup_processor(void)
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sprintf(init_utsname()->machine, ELF_PLATFORM);
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elf_hwcap = 0;
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/*
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* ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
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* The blocks we test below represent incremental functionality
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* for non-negative values. Negative values are reserved.
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*/
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features = read_cpuid(ID_AA64ISAR0_EL1);
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block = (features >> 4) & 0xf;
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if (!(block & 0x8)) {
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switch (block) {
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default:
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case 2:
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elf_hwcap |= HWCAP_PMULL;
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case 1:
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elf_hwcap |= HWCAP_AES;
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case 0:
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break;
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}
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}
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block = (features >> 8) & 0xf;
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if (block && !(block & 0x8))
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elf_hwcap |= HWCAP_SHA1;
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block = (features >> 12) & 0xf;
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if (block && !(block & 0x8))
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elf_hwcap |= HWCAP_SHA2;
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block = (features >> 16) & 0xf;
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if (block && !(block & 0x8))
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elf_hwcap |= HWCAP_CRC32;
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}
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static void __init setup_machine_fdt(phys_addr_t dt_phys)
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@ -280,6 +312,11 @@ static const char *hwcap_str[] = {
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"fp",
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"asimd",
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"evtstrm",
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"aes",
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"pmull",
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"sha1",
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"sha2",
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"crc32",
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NULL
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};
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