forked from luck/tmp_suning_uos_patched
powerpc/85xx: Rework P1020RDB device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
4de0e39cb8
commit
4e36afa7c5
174
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
Normal file
174
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
Normal file
@ -0,0 +1,174 @@
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/*
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* P1020/P1011 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
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||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
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* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
|
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* later version.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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&lbc {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
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interrupts = <19 2 0 0>;
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};
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/* controller at 0x9000 */
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&pci0 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0 255>;
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clock-frequency = <33333333>;
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interrupts = <16 2 0 0>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <16 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
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0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
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0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
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0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
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>;
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};
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};
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/* controller at 0xa000 */
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&pci1 {
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0 255>;
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clock-frequency = <33333333>;
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interrupts = <16 2 0 0>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <16 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
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0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
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0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
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0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
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>;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,p1020-immr", "simple-bus";
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,p1020-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <16 2 0 0>;
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};
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memory-controller@2000 {
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compatible = "fsl,p1020-memory-controller";
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reg = <0x2000 0x1000>;
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interrupts = <16 2 0 0>;
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};
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/include/ "pq3-i2c-0.dtsi"
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/include/ "pq3-i2c-1.dtsi"
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/include/ "pq3-duart-0.dtsi"
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/include/ "pq3-espi-0.dtsi"
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spi@7000 {
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fsl,espi-num-chipselects = <4>;
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};
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/include/ "pq3-gpio-0.dtsi"
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L2: l2-cache-controller@20000 {
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compatible = "fsl,p1020-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x40000>; // L2,256K
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interrupts = <16 2 0 0>;
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};
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/include/ "pq3-dma-0.dtsi"
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/include/ "pq3-usb2-dr-0.dtsi"
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/include/ "pq3-usb2-dr-1.dtsi"
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/include/ "pq3-esdhc-0.dtsi"
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/include/ "pq3-sec3.3-0.dtsi"
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/include/ "pq3-mpic.dtsi"
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/include/ "pq3-mpic-timer-B.dtsi"
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/include/ "pq3-etsec2-0.dtsi"
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enet0: enet0_grp2: ethernet@b0000 {
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};
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/include/ "pq3-etsec2-1.dtsi"
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enet1: enet1_grp2: ethernet@b1000 {
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};
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/include/ "pq3-etsec2-2.dtsi"
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enet2: enet2_grp2: ethernet@b2000 {
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};
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global-utilities@e0000 {
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compatible = "fsl,p1020-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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};
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/include/ "pq3-etsec2-grp2-0.dtsi"
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/include/ "pq3-etsec2-grp2-1.dtsi"
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/include/ "pq3-etsec2-grp2-2.dtsi"
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68
arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
Normal file
68
arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
Normal file
@ -0,0 +1,68 @@
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/*
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* P1020/P1011 Silicon/SoC Device Tree Source (pre include)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
|
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* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
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||||
*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
|
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* Foundation, either version 2 of that License or (at your option) any
|
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/ {
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compatible = "fsl,P1020";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,P1020@0 {
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device_type = "cpu";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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PowerPC,P1020@1 {
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device_type = "cpu";
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reg = <0x1>;
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next-level-cache = <&L2>;
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};
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};
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};
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@ -9,245 +9,26 @@
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* option) any later version.
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*/
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/include/ "p1020si.dtsi"
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/include/ "fsl/p1020si-pre.dtsi"
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/ {
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model = "fsl,P1020RDB";
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compatible = "fsl,P1020RDB";
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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memory {
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device_type = "memory";
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};
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localbus@ffe05000 {
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board_lbc: lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
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ranges = <0x0 0x0 0x0 0xef000000 0x01000000
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0x1 0x0 0x0 0xffa00000 0x00040000
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0x2 0x0 0x0 0xffb00000 0x00020000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x1000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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/* This location must not be altered */
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/* 256KB for Vitesse 7385 Switch firmware */
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reg = <0x0 0x00040000>;
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label = "NOR (RO) Vitesse-7385 Firmware";
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read-only;
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};
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partition@40000 {
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/* 256KB for DTB Image */
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reg = <0x00040000 0x00040000>;
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label = "NOR (RO) DTB Image";
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read-only;
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};
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partition@80000 {
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/* 3.5 MB for Linux Kernel Image */
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reg = <0x00080000 0x00380000>;
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label = "NOR (RO) Linux Kernel Image";
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read-only;
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};
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partition@400000 {
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/* 11MB for JFFS2 based Root file System */
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reg = <0x00400000 0x00b00000>;
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label = "NOR (RW) JFFS2 Root File System";
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};
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partition@f00000 {
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/* This location must not be altered */
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/* 512KB for u-boot Bootloader Image */
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/* 512KB for u-boot Environment Variables */
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reg = <0x00f00000 0x00100000>;
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label = "NOR (RO) U-Boot Image";
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read-only;
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};
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p1020-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x1 0x0 0x40000>;
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partition@0 {
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/* This location must not be altered */
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/* 1MB for u-boot Bootloader Image */
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reg = <0x0 0x00100000>;
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label = "NAND (RO) U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 1MB for DTB Image */
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reg = <0x00100000 0x00100000>;
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label = "NAND (RO) DTB Image";
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read-only;
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};
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partition@200000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00200000 0x00400000>;
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label = "NAND (RO) Linux Kernel Image";
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read-only;
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};
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||||
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partition@600000 {
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||||
/* 4MB for Compressed Root file System Image */
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reg = <0x00600000 0x00400000>;
|
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label = "NAND (RO) Compressed RFS Image";
|
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read-only;
|
||||
};
|
||||
|
||||
partition@a00000 {
|
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/* 7MB for JFFS2 based Root file System */
|
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reg = <0x00a00000 0x00700000>;
|
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label = "NAND (RW) JFFS2 Root File System";
|
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};
|
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partition@1100000 {
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/* 15MB for JFFS2 based Root file System */
|
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reg = <0x01100000 0x00f00000>;
|
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label = "NAND (RW) Writable User area";
|
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};
|
||||
};
|
||||
|
||||
L2switch@2,0 {
|
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#address-cells = <1>;
|
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#size-cells = <1>;
|
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compatible = "vitesse-7385";
|
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reg = <0x2 0x0 0x20000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
i2c@3000 {
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
|
||||
partition@u-boot {
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00080000>;
|
||||
label = "u-boot";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@dtb {
|
||||
/* 512KB for DTB Image */
|
||||
reg = <0x00080000 0x00080000>;
|
||||
label = "dtb";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@kernel {
|
||||
/* 4MB for Linux Kernel Image */
|
||||
reg = <0x00100000 0x00400000>;
|
||||
label = "kernel";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@fs {
|
||||
/* 4MB for Compressed RFS Image */
|
||||
reg = <0x00500000 0x00400000>;
|
||||
label = "file system";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@jffs-fs {
|
||||
/* 7MB for JFFS2 based RFS */
|
||||
reg = <0x00900000 0x00700000>;
|
||||
label = "file system jffs2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <2 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@25000 {
|
||||
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy0>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
|
||||
};
|
||||
|
||||
enet2: ethernet@b2000 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
/* USB2 is shared with localbus, so it must be disabled
|
||||
by default. We can't put 'status = "disabled";' here
|
||||
since U-Boot doesn't clear the status property when
|
||||
it enables USB2. OTOH, U-Boot does create a new node
|
||||
when there isn't any. So, just comment it out.
|
||||
usb@23000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
*/
|
||||
|
||||
board_soc: soc: soc@ffe00000 {
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
@ -280,3 +61,6 @@ pcie@0 {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "p1020rdb.dtsi"
|
||||
/include/ "fsl/p1020si-post.dtsi"
|
||||
|
||||
242
arch/powerpc/boot/dts/p1020rdb.dtsi
Normal file
242
arch/powerpc/boot/dts/p1020rdb.dtsi
Normal file
@ -0,0 +1,242 @@
|
||||
/*
|
||||
* P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&board_lbc {
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 256KB for Vitesse 7385 Switch firmware */
|
||||
reg = <0x0 0x00040000>;
|
||||
label = "NOR (RO) Vitesse-7385 Firmware";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
/* 256KB for DTB Image */
|
||||
reg = <0x00040000 0x00040000>;
|
||||
label = "NOR (RO) DTB Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
/* 3.5 MB for Linux Kernel Image */
|
||||
reg = <0x00080000 0x00380000>;
|
||||
label = "NOR (RO) Linux Kernel Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
/* 11MB for JFFS2 based Root file System */
|
||||
reg = <0x00400000 0x00b00000>;
|
||||
label = "NOR (RW) JFFS2 Root File System";
|
||||
};
|
||||
|
||||
partition@f00000 {
|
||||
/* This location must not be altered */
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
/* 512KB for u-boot Environment Variables */
|
||||
reg = <0x00f00000 0x00100000>;
|
||||
label = "NOR (RO) U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1020-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <0x1 0x0 0x40000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND (RO) U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00100000 0x00100000>;
|
||||
label = "NAND (RO) DTB Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
/* 4MB for Linux Kernel Image */
|
||||
reg = <0x00200000 0x00400000>;
|
||||
label = "NAND (RO) Linux Kernel Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@600000 {
|
||||
/* 4MB for Compressed Root file System Image */
|
||||
reg = <0x00600000 0x00400000>;
|
||||
label = "NAND (RO) Compressed RFS Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@a00000 {
|
||||
/* 7MB for JFFS2 based Root file System */
|
||||
reg = <0x00a00000 0x00700000>;
|
||||
label = "NAND (RW) JFFS2 Root File System";
|
||||
};
|
||||
|
||||
partition@1100000 {
|
||||
/* 15MB for JFFS2 based Root file System */
|
||||
reg = <0x01100000 0x00f00000>;
|
||||
label = "NAND (RW) Writable User area";
|
||||
};
|
||||
};
|
||||
|
||||
L2switch@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "vitesse-7385";
|
||||
reg = <0x2 0x0 0x20000>;
|
||||
};
|
||||
};
|
||||
|
||||
&board_soc {
|
||||
i2c@3000 {
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
|
||||
partition@u-boot {
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00080000>;
|
||||
label = "u-boot";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@dtb {
|
||||
/* 512KB for DTB Image */
|
||||
reg = <0x00080000 0x00080000>;
|
||||
label = "dtb";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@kernel {
|
||||
/* 4MB for Linux Kernel Image */
|
||||
reg = <0x00100000 0x00400000>;
|
||||
label = "kernel";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@fs {
|
||||
/* 4MB for Compressed RFS Image */
|
||||
reg = <0x00500000 0x00400000>;
|
||||
label = "file system";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@jffs-fs {
|
||||
/* 7MB for JFFS2 based RFS */
|
||||
reg = <0x00900000 0x00700000>;
|
||||
label = "file system jffs2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
/* USB2 is shared with localbus, so it must be disabled
|
||||
by default. We can't put 'status = "disabled";' here
|
||||
since U-Boot doesn't clear the status property when
|
||||
it enables USB2. OTOH, U-Boot does create a new node
|
||||
when there isn't any. So, just comment it out.
|
||||
usb@23000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
*/
|
||||
|
||||
mdio@24000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <3 1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <2 1>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@25000 {
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy0>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
enet2: ethernet@b2000 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
};
|
||||
@ -1,407 +0,0 @@
|
||||
/*
|
||||
* P1020si Device Tree Source
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
compatible = "fsl,P1020";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P1020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0 0xffe05000 0 0x1000>;
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
soc@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1020-immr", "simple-bus";
|
||||
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1020-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1020-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2 0 0>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2 0 0>;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,p1020-espi", "fsl,mpc8536-espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2 0 0>;
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
gpio: gpio-controller@f000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8572-gpio";
|
||||
reg = <0xf000 0x100>;
|
||||
interrupts = <47 0x2 0 0>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <20 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <21 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <22 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <23 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-mdio";
|
||||
reg = <0x24000 0x1000 0xb0030 0x4>;
|
||||
|
||||
};
|
||||
|
||||
mdio@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-tbi";
|
||||
reg = <0x25000 0x1000 0xb1030 0x4>;
|
||||
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb0000 0x1000>;
|
||||
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
|
||||
};
|
||||
|
||||
queue-group@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb4000 0x1000>;
|
||||
interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb1000 0x1000>;
|
||||
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
|
||||
};
|
||||
|
||||
queue-group@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb5000 0x1000>;
|
||||
interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@b2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
|
||||
queue-group@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb2000 0x1000>;
|
||||
interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
|
||||
};
|
||||
|
||||
queue-group@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb6000 0x1000>;
|
||||
interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x22000 0x1000>;
|
||||
interrupts = <28 0x2 0 0>;
|
||||
};
|
||||
|
||||
/* USB2 is shared with localbus, so it must be disabled
|
||||
by default. We can't put 'status = "disabled";' here
|
||||
since U-Boot doesn't clear the status property when
|
||||
it enables USB2. OTOH, U-Boot does create a new node
|
||||
when there isn't any. So, just comment it out.
|
||||
usb@23000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
interrupts = <46 0x2 0 0>;
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
*/
|
||||
|
||||
sdhci@2e000 {
|
||||
compatible = "fsl,p1020-esdhc", "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2 0 0>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
|
||||
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
|
||||
"fsl,sec2.0";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <45 2 0 0 58 2 0 0>;
|
||||
fsl,num-channels = <4>;
|
||||
fsl,channel-fifo-len = <24>;
|
||||
fsl,exec-units-mask = <0x97c>;
|
||||
fsl,descriptor-types-mask = <0x3a30abf>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <4>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
timer@41100 {
|
||||
compatible = "fsl,mpic-global-timer";
|
||||
reg = <0x41100 0x100 0x41300 4>;
|
||||
interrupts = <0 0 3 0
|
||||
1 0 3 0
|
||||
2 0 3 0
|
||||
3 0 3 0>;
|
||||
};
|
||||
|
||||
timer@42100 {
|
||||
compatible = "fsl,mpic-global-timer";
|
||||
reg = <0x42100 0x100 0x42300 4>;
|
||||
interrupts = <4 0 3 0
|
||||
5 0 3 0
|
||||
6 0 3 0
|
||||
7 0 3 0>;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,p1020-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0 0 0
|
||||
0xe1 0 0 0
|
||||
0xe2 0 0 0
|
||||
0xe3 0 0 0
|
||||
0xe4 0 0 0
|
||||
0xe5 0 0 0
|
||||
0xe6 0 0 0
|
||||
0xe7 0 0 0>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities block
|
||||
compatible = "fsl,p1020-guts","fsl,p2020-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe09000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1
|
||||
>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci1: pcie@ffe0a000 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user