forked from luck/tmp_suning_uos_patched
ARM: footbridge: convert to clockevents/clocksource
The Footbridge platforms have some reasonable timers in the host bridge, which we use for most footbridge-based platforms. However, NetWinder's clock these using a spread-spectrum clock which makes them too unstable for time keeping. So we have to rely on the PIT. Convert both Footbridge timers and PIT timers to use the clocksource and clockevent infrastructure. Tested on Netwinder. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
5f2c1b30c7
commit
4e8d76373c
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@ -346,7 +346,7 @@ config ARCH_FOOTBRIDGE
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bool "FootBridge"
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select CPU_SA110
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select FOOTBRIDGE
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select ARCH_USES_GETTIMEOFFSET
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select GENERIC_CLOCKEVENTS
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help
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Support for systems based on the DC21285 companion chip
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("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
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@ -4,10 +4,11 @@
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* Copyright (C) 1998 Russell King.
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* Copyright (C) 1998 Phil Blundell
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*/
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <asm/irq.h>
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@ -16,32 +17,76 @@
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#include "common.h"
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/*
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* Footbridge timer 1 support.
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*/
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static unsigned long timer1_latch;
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static unsigned long timer1_gettimeoffset (void)
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static cycle_t cksrc_dc21285_read(struct clocksource *cs)
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{
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unsigned long value = timer1_latch - *CSR_TIMER1_VALUE;
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return ((tick_nsec / 1000) * value) / timer1_latch;
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return cs->mask - *CSR_TIMER2_VALUE;
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}
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static irqreturn_t
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timer1_interrupt(int irq, void *dev_id)
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static int cksrc_dc21285_enable(struct clocksource *cs)
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{
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*CSR_TIMER2_LOAD = cs->mask;
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*CSR_TIMER2_CLR = 0;
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*CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
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return 0;
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}
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static int cksrc_dc21285_disable(struct clocksource *cs)
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{
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*CSR_TIMER2_CNTL = 0;
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}
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static struct clocksource cksrc_dc21285 = {
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.name = "dc21285_timer2",
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.rating = 200,
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.read = cksrc_dc21285_read,
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.enable = cksrc_dc21285_enable,
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.disable = cksrc_dc21285_disable,
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.mask = CLOCKSOURCE_MASK(24),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
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struct clock_event_device *c)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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*CSR_TIMER1_CLR = 0;
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*CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
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*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
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TIMER_CNTL_DIV16;
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break;
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default:
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*CSR_TIMER1_CNTL = 0;
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break;
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}
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}
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static struct clock_event_device ckevt_dc21285 = {
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.name = "dc21285_timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.rating = 200,
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.irq = IRQ_TIMER1,
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.set_mode = ckevt_dc21285_set_mode,
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};
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static irqreturn_t timer1_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *ce = dev_id;
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*CSR_TIMER1_CLR = 0;
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timer_tick();
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ce->event_handler(ce);
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return IRQ_HANDLED;
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}
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static struct irqaction footbridge_timer_irq = {
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.name = "Timer1 timer tick",
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.name = "dc21285_timer1",
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.handler = timer1_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.dev_id = &ckevt_dc21285,
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};
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/*
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@ -49,16 +94,19 @@ static struct irqaction footbridge_timer_irq = {
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*/
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static void __init footbridge_timer_init(void)
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{
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timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
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struct clock_event_device *ce = &ckevt_dc21285;
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*CSR_TIMER1_CLR = 0;
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*CSR_TIMER1_LOAD = timer1_latch;
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*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16;
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clocksource_register_hz(&cksrc_dc21285, (mem_fclk_21285 + 8) / 16);
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setup_irq(IRQ_TIMER1, &footbridge_timer_irq);
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setup_irq(ce->irq, &footbridge_timer_irq);
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clockevents_calc_mult_shift(ce, mem_fclk_21285, 5);
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ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce);
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ce->min_delta_ns = clockevent_delta2ns(0x000004, ce);
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clockevents_register_device(ce);
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}
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struct sys_timer footbridge_timer = {
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.init = footbridge_timer_init,
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.offset = timer1_gettimeoffset,
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};
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@ -4,10 +4,13 @@
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* Copyright (C) 1998 Russell King.
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* Copyright (C) 1998 Phil Blundell
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*/
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/timex.h>
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#include <asm/irq.h>
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@ -15,77 +18,115 @@
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#include "common.h"
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/*
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* ISA timer tick support
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*/
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#define mSEC_10_from_14 ((14318180 + 100) / 200)
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#define PIT_MODE 0x43
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#define PIT_CH0 0x40
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static unsigned long isa_gettimeoffset(void)
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#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ)
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static cycle_t pit_read(struct clocksource *cs)
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{
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unsigned long flags;
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static int old_count;
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static u32 old_jifs;
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int count;
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u32 jifs;
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static int count_p = (mSEC_10_from_14/6); /* for the first call after boot */
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static unsigned long jiffies_p = 0;
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raw_local_irq_save(flags);
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/*
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* cache volatile jiffies temporarily; we have IRQs turned off.
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*/
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unsigned long jiffies_t;
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jifs = jiffies;
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outb_p(0x00, PIT_MODE); /* latch the count */
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count = inb_p(PIT_CH0); /* read the latched count */
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count |= inb_p(PIT_CH0) << 8;
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/* timer count may underflow right here */
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outb_p(0x00, 0x43); /* latch the count ASAP */
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if (count > old_count && jifs == old_jifs)
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count = old_count;
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count = inb_p(0x40); /* read the latched count */
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old_count = count;
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old_jifs = jifs;
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/*
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* We do this guaranteed double memory access instead of a _p
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* postfix in the previous port access. Wheee, hackady hack
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*/
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jiffies_t = jiffies;
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raw_local_irq_restore(flags);
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count |= inb_p(0x40) << 8;
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count = (PIT_LATCH - 1) - count;
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/* Detect timer underflows. If we haven't had a timer tick since
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the last time we were called, and time is apparently going
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backwards, the counter must have wrapped during this routine. */
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if ((jiffies_t == jiffies_p) && (count > count_p))
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count -= (mSEC_10_from_14/6);
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else
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jiffies_p = jiffies_t;
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count_p = count;
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count = (((mSEC_10_from_14/6)-1) - count) * (tick_nsec / 1000);
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count = (count + (mSEC_10_from_14/6)/2) / (mSEC_10_from_14/6);
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return count;
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return (cycle_t)(jifs * PIT_LATCH) + count;
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}
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static irqreturn_t
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isa_timer_interrupt(int irq, void *dev_id)
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static struct clocksource pit_cs = {
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.name = "pit",
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.rating = 110,
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.read = pit_read,
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.mask = CLOCKSOURCE_MASK(32),
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};
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static void pit_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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timer_tick();
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unsigned long flags;
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raw_local_irq_save(flags);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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outb_p(0x34, PIT_MODE);
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outb_p(PIT_LATCH & 0xff, PIT_CH0);
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outb_p(PIT_LATCH >> 8, PIT_CH0);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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outb_p(0x30, PIT_MODE);
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outb_p(0, PIT_CH0);
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outb_p(0, PIT_CH0);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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local_irq_restore(flags);
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}
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static int pit_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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return 0;
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}
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static struct clock_event_device pit_ce = {
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.name = "pit",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = pit_set_mode,
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.set_next_event = pit_set_next_event,
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.shift = 32,
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};
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static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *ce = dev_id;
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ce->event_handler(ce);
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return IRQ_HANDLED;
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}
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static struct irqaction isa_timer_irq = {
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.name = "ISA timer tick",
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.handler = isa_timer_interrupt,
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static struct irqaction pit_timer_irq = {
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.name = "pit",
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.handler = pit_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.dev_id = &pit_ce,
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};
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static void __init isa_timer_init(void)
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{
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/* enable PIT timer */
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/* set for periodic (4) and LSB/MSB write (0x30) */
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outb(0x34, 0x43);
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outb((mSEC_10_from_14/6) & 0xFF, 0x40);
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outb((mSEC_10_from_14/6) >> 8, 0x40);
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pit_ce.cpumask = cpumask_of(smp_processor_id());
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pit_ce.mult = div_sc(PIT_TICK_RATE, NSEC_PER_SEC, pit_ce.shift);
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pit_ce.max_delta_ns = clockevent_delta2ns(0x7fff, &pit_ce);
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pit_ce.min_delta_ns = clockevent_delta2ns(0x000f, &pit_ce);
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setup_irq(IRQ_ISA_TIMER, &isa_timer_irq);
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clocksource_register_hz(&pit_cs, PIT_TICK_RATE);
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setup_irq(pit_ce.irq, &pit_timer_irq);
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clockevents_register_device(&pit_ce);
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}
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struct sys_timer isa_timer = {
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.init = isa_timer_init,
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.offset = isa_gettimeoffset,
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};
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