AcoSail/kernel_optimize_test
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clk: pistachio: Add a pll_lock() helper for clarity

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This commit adds a pll_lock() helper making the code more readable.
Cosmetic change only, no functionality changes.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Ezequiel Garcia 2015-05-26 19:01:07 -03:00 committed by Stephen Boyd
parent 24c65a02b2
commit 4f4adfbf8e
1 changed files with 8 additions and 4 deletions
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12
drivers/clk/pistachio/clk-pll.c
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@ -67,6 +67,12 @@ static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)
writel(val, pll->base + reg);
}
static inline void pll_lock(struct pistachio_clk_pll *pll)
{
while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
cpu_relax();
}
static inline u32 do_div_round_closest(u64 dividend, u32 divisor)
{
dividend += divisor / 2;
@ -178,8 +184,7 @@ static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,
(params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);
pll_writel(pll, val, PLL_CTRL2);
while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
cpu_relax();
pll_lock(pll);
if (!was_enabled)
pll_gf40lp_frac_disable(hw);
@ -288,8 +293,7 @@ static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate,
(params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT);
pll_writel(pll, val, PLL_CTRL1);
while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
cpu_relax();
pll_lock(pll);
if (!was_enabled)
pll_gf40lp_laint_disable(hw);