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ARM: tegra: add support for new clock framework features

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Add support for new clock framework features implemented in tegra30.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Peter De Schrijver 2012-01-09 05:35:11 +00:00 committed by Olof Johansson
parent caa4868ee0
commit 4fccf75ba3
3 changed files with 46 additions and 0 deletions
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22
arch/arm/mach-tegra/clock.c
View File

@ -399,6 +399,28 @@ void tegra_periph_reset_assert(struct clk *c)
}
EXPORT_SYMBOL(tegra_periph_reset_assert);
/* Several extended clock configuration bits (e.g., clock routing, clock
* phase control) are included in PLL and peripheral clock source
* registers. */
int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
{
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&c->spinlock, flags);
if (!c->ops || !c->ops->clk_cfg_ex) {
ret = -ENOSYS;
goto out;
}
ret = c->ops->clk_cfg_ex(c, p, setting);
out:
spin_unlock_irqrestore(&c->spinlock, flags);
return ret;
}
#ifdef CONFIG_DEBUG_FS
static int __clk_lock_all_spinlocks(void)

14
arch/arm/mach-tegra/clock.h
View File

@ -24,6 +24,8 @@
#include <linux/list.h>
#include <linux/spinlock.h>
#include <mach/clk.h>
#define DIV_BUS (1 << 0)
#define DIV_U71 (1 << 1)
#define DIV_U71_FIXED (1 << 2)
@ -39,7 +41,16 @@
#define PERIPH_MANUAL_RESET (1 << 12)
#define PLL_ALT_MISC_REG (1 << 13)
#define PLLU (1 << 14)
#define PLLX (1 << 15)
#define MUX_PWM (1 << 16)
#define MUX8 (1 << 17)
#define DIV_U71_UART (1 << 18)
#define MUX_CLK_OUT (1 << 19)
#define PLLM (1 << 20)
#define DIV_U71_INT (1 << 21)
#define DIV_U71_IDLE (1 << 22)
#define ENABLE_ON_INIT (1 << 28)
#define PERIPH_ON_APB (1 << 29)
struct clk;
@ -65,6 +76,8 @@ struct clk_ops {
int (*set_rate)(struct clk *, unsigned long);
long (*round_rate)(struct clk *, unsigned long);
void (*reset)(struct clk *, bool);
int (*clk_cfg_ex)(struct clk *,
enum tegra_clk_ex_param, u32);
};
enum clk_state {
@ -114,6 +127,7 @@ struct clk {
unsigned long vco_max;
const struct clk_pll_freq_table *freq_table;
int lock_delay;
unsigned long fixed_rate;
} pll;
struct {
u32 sel;

10
arch/arm/mach-tegra/include/mach/clk.h
View File

@ -22,10 +22,20 @@
struct clk;
enum tegra_clk_ex_param {
TEGRA_CLK_VI_INP_SEL,
TEGRA_CLK_DTV_INVERT,
TEGRA_CLK_NAND_PAD_DIV2_ENB,
TEGRA_CLK_PLLD_CSI_OUT_ENB,
TEGRA_CLK_PLLD_DSI_OUT_ENB,
TEGRA_CLK_PLLD_MIPI_MUX_SEL,
};
void tegra_periph_reset_deassert(struct clk *c);
void tegra_periph_reset_assert(struct clk *c);
unsigned long clk_get_rate_all_locked(struct clk *c);
void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
#endif