forked from luck/tmp_suning_uos_patched
ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it for eval and disco boards
Synopsys GMAC 4.10 is used. And Phy mode for eval and disco is RMII with PHY SMSC LAN8742 Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -173,6 +173,21 @@ pins {
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};
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};
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ethernet_rmii: rmii@0 {
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pins {
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pinmux = <STM32_PINMUX('G', 11, AF11)>,
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<STM32_PINMUX('G', 13, AF11)>,
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<STM32_PINMUX('G', 12, AF11)>,
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<STM32_PINMUX('C', 4, AF11)>,
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<STM32_PINMUX('C', 5, AF11)>,
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<STM32_PINMUX('A', 7, AF11)>,
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<STM32_PINMUX('C', 1, AF11)>,
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<STM32_PINMUX('A', 2, AF11)>,
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<STM32_PINMUX('A', 1, AF11)>;
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slew-rate = <2>;
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};
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};
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usart1_pins: usart1@0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
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@ -511,6 +511,19 @@ adc3: adc@0 {
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status = "disabled";
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};
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};
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mac: ethernet@40028000 {
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compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
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reg = <0x40028000 0x8000>;
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reg-names = "stmmaceth";
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interrupts = <61>;
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interrupt-names = "macirq";
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clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
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clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
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st,syscon = <&syscfg 0x4>;
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snps,pbl = <8>;
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status = "disabled";
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};
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};
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};
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@ -66,6 +66,23 @@ &clk_hse {
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clock-frequency = <25000000>;
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};
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&mac {
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status = "disabled";
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pinctrl-0 = <ðernet_rmii>;
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pinctrl-names = "default";
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phy-mode = "rmii";
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phy-handle = <&phy0>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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&usart2 {
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pinctrl-0 = <&usart2_pins>;
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pinctrl-names = "default";
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@ -104,6 +104,23 @@ &rtc {
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status = "okay";
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};
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&mac {
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status = "disabled";
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pinctrl-0 = <ðernet_rmii>;
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pinctrl-names = "default";
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phy-mode = "rmii";
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phy-handle = <&phy0>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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&usart1 {
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pinctrl-0 = <&usart1_pins>;
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pinctrl-names = "default";
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