forked from luck/tmp_suning_uos_patched
parisc: Add native high-resolution sched_clock() implementation
Add a native implementation for the sched_clock() function which utilizes the processor-internal cycle counter (Control Register 16) as high-resolution time source. With this patch we now get much more fine-grained resolutions in various in-kernel time measurements (e.g. when viewing the function tracing logs), and probably a more accurate scheduling on SMP systems. There are a few specific implementation details in this patch: 1. On a 32bit kernel we emulate the higher 32bits of the required 64-bit resolution of sched_clock() by increasing a per-cpu counter at every wrap-around of the 32bit cycle counter. 2. In a SMP system, the cycle counters of the various CPUs are not syncronized (similiar to the TSC in a x86_64 system). To cope with this we define HAVE_UNSTABLE_SCHED_CLOCK and let the upper layers do the adjustment work. 3. Since we need HAVE_UNSTABLE_SCHED_CLOCK, we need to provide a cmpxchg64() function even on a 32-bit kernel. 4. A 64-bit SMP kernel which is started on a UP system will mark the sched_clock() implementation as "stable", which means that we don't expect any jumps in the returned counter. This is true because we then run only on one CPU. Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Helge Deller
parent
64e2a42bca
commit
54b6680090
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@ -33,6 +33,7 @@ config PARISC
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select HAVE_ARCH_AUDITSYSCALL
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select HAVE_ARCH_SECCOMP_FILTER
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select HAVE_ARCH_TRACEHOOK
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select HAVE_UNSTABLE_SCHED_CLOCK if (SMP || !64BIT)
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select ARCH_NO_COHERENT_DMA_MMAP
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select CPU_NO_EFFICIENT_FFS
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@ -52,8 +52,7 @@ extern void __cmpxchg_called_with_bad_pointer(void);
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/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */
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extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old,
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unsigned int new_);
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extern unsigned long __cmpxchg_u64(volatile unsigned long *ptr,
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unsigned long old, unsigned long new_);
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extern u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new_);
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/* don't worry...optimizer will get rid of most of this */
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static inline unsigned long
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@ -61,7 +60,7 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
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{
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switch (size) {
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#ifdef CONFIG_64BIT
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case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
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case 8: return __cmpxchg_u64((u64 *)ptr, old, new_);
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#endif
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case 4: return __cmpxchg_u32((unsigned int *)ptr,
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(unsigned int)old, (unsigned int)new_);
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@ -86,7 +85,7 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
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{
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switch (size) {
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#ifdef CONFIG_64BIT
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case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
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case 8: return __cmpxchg_u64((u64 *)ptr, old, new_);
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#endif
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case 4: return __cmpxchg_u32(ptr, old, new_);
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default:
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@ -111,4 +110,6 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
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#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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#endif
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#define cmpxchg64(ptr, o, n) __cmpxchg_u64(ptr, o, n)
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#endif /* _ASM_PARISC_CMPXCHG_H_ */
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@ -38,6 +38,18 @@
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static unsigned long clocktick __read_mostly; /* timer cycles per tick */
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#ifndef CONFIG_64BIT
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/*
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* The processor-internal cycle counter (Control Register 16) is used as time
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* source for the sched_clock() function. This register is 64bit wide on a
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* 64-bit kernel and 32bit on a 32-bit kernel. Since sched_clock() always
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* requires a 64bit counter we emulate on the 32-bit kernel the higher 32bits
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* with a per-cpu variable which we increase every time the counter
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* wraps-around (which happens every ~4 secounds).
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*/
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static DEFINE_PER_CPU(unsigned long, cr16_high_32_bits);
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#endif
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/*
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* We keep time on PA-RISC Linux by using the Interval Timer which is
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* a pair of registers; one is read-only and one is write-only; both
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@ -108,6 +120,12 @@ irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
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*/
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mtctl(next_tick, 16);
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#if !defined(CONFIG_64BIT)
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/* check for overflow on a 32bit kernel (every ~4 seconds). */
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if (unlikely(next_tick < now))
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this_cpu_inc(cr16_high_32_bits);
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#endif
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/* Skip one clocktick on purpose if we missed next_tick.
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* The new CR16 must be "later" than current CR16 otherwise
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* itimer would not fire until CR16 wrapped - e.g 4 seconds
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@ -219,6 +237,12 @@ void __init start_cpu_itimer(void)
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unsigned int cpu = smp_processor_id();
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unsigned long next_tick = mfctl(16) + clocktick;
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#if defined(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK) && defined(CONFIG_64BIT)
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/* With multiple 64bit CPUs online, the cr16's are not syncronized. */
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if (cpu != 0)
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clear_sched_clock_stable();
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#endif
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mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */
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per_cpu(cpu_data, cpu).it_value = next_tick;
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@ -246,15 +270,52 @@ void read_persistent_clock(struct timespec *ts)
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}
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}
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/*
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* sched_clock() framework
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*/
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static u32 cyc2ns_mul __read_mostly;
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static u32 cyc2ns_shift __read_mostly;
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u64 sched_clock(void)
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{
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u64 now;
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/* Get current cycle counter (Control Register 16). */
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#ifdef CONFIG_64BIT
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now = mfctl(16);
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#else
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now = mfctl(16) + (((u64) this_cpu_read(cr16_high_32_bits)) << 32);
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#endif
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/* return the value in ns (cycles_2_ns) */
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return mul_u64_u32_shr(now, cyc2ns_mul, cyc2ns_shift);
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}
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/*
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* timer interrupt and sched_clock() initialization
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*/
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void __init time_init(void)
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{
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unsigned long current_cr16_khz;
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current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */
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clocktick = (100 * PAGE0->mem_10msec) / HZ;
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/* calculate mult/shift values for cr16 */
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clocks_calc_mult_shift(&cyc2ns_mul, &cyc2ns_shift, current_cr16_khz,
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NSEC_PER_MSEC, 0);
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#if defined(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK) && defined(CONFIG_64BIT)
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/* At bootup only one 64bit CPU is online and cr16 is "stable" */
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set_sched_clock_stable();
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#endif
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start_cpu_itimer(); /* get CPU 0 started */
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/* register at clocksource framework */
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current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */
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clocksource_register_khz(&clocksource_cr16, current_cr16_khz);
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}
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@ -55,11 +55,10 @@ unsigned long __xchg8(char x, char *ptr)
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}
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#ifdef CONFIG_64BIT
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unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsigned long new)
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u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new)
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{
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unsigned long flags;
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unsigned long prev;
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u64 prev;
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_atomic_spin_lock_irqsave(ptr, flags);
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if ((prev = *ptr) == old)
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@ -67,7 +66,6 @@ unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsi
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_atomic_spin_unlock_irqrestore(ptr, flags);
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return prev;
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}
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#endif
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unsigned long __cmpxchg_u32(volatile unsigned int *ptr, unsigned int old, unsigned int new)
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{
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