forked from luck/tmp_suning_uos_patched
powerpc/fsl: Setup PCI inbound window based on actual amount of memory
Previouslly we just always set the inbound window to 2G. This was broken for systems with >2G. If a system has >=4G we will need SWIOTLB support to handle that case. We now allocate PCICSRBAR/PEXCSRBAR right below the lowest PCI outbound address for MMIO or the 4G boundary (if the lowest PCI address is above 4G). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
01af9507ff
commit
54c181935d
@ -23,6 +23,8 @@
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/lmb.h>
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#include <linux/log2.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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@ -96,7 +98,13 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
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struct resource *rsrc)
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{
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struct ccsr_pci __iomem *pci;
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int i, j, n;
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int i, j, n, mem_log, win_idx = 2;
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u64 mem, sz, paddr_hi = 0;
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u64 paddr_lo = ULLONG_MAX;
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u32 pcicsrbar = 0, pcicsrbar_sz;
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u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
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char *name = hose->dn->full_name;
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
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@ -117,6 +125,9 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
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if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
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continue;
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paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
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paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
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n = setup_one_atmu(pci, j, &hose->mem_resources[i],
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hose->pci_mem_offset);
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@ -147,14 +158,105 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
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}
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}
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/* Setup 2G inbound Memory Window @ 1 */
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out_be32(&pci->piw[2].pitar, 0x00000000);
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out_be32(&pci->piw[2].piwbar,0x00000000);
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out_be32(&pci->piw[2].piwar, PIWAR_2G);
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/* convert to pci address space */
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paddr_hi -= hose->pci_mem_offset;
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paddr_lo -= hose->pci_mem_offset;
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/* Save the base address and size covered by inbound window mappings */
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hose->dma_window_base_cur = 0x00000000;
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hose->dma_window_size = 0x80000000;
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if (paddr_hi == paddr_lo) {
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pr_err("%s: No outbound window space\n", name);
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return ;
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}
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if (paddr_lo == 0) {
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pr_err("%s: No space for inbound window\n", name);
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return ;
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}
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/* setup PCSRBAR/PEXCSRBAR */
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early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
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early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
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pcicsrbar_sz = ~pcicsrbar_sz + 1;
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if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
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(paddr_lo > 0x100000000ull))
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pcicsrbar = 0x100000000ull - pcicsrbar_sz;
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else
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pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
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early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
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paddr_lo = min(paddr_lo, (u64)pcicsrbar);
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pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
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/* Setup inbound mem window */
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mem = lmb_end_of_DRAM();
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sz = min(mem, paddr_lo);
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mem_log = __ilog2_u64(sz);
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/* PCIe can overmap inbound & outbound since RX & TX are separated */
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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/* Size window to exact size if power-of-two or one size up */
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if ((1ull << mem_log) != mem) {
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if ((1ull << mem_log) > mem)
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pr_info("%s: Setting PCI inbound window "
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"greater than memory size\n", name);
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mem_log++;
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}
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piwar |= (mem_log - 1);
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/* Setup inbound memory window */
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out_be32(&pci->piw[win_idx].pitar, 0x00000000);
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out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
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out_be32(&pci->piw[win_idx].piwar, piwar);
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win_idx--;
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hose->dma_window_base_cur = 0x00000000;
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hose->dma_window_size = (resource_size_t)sz;
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} else {
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u64 paddr = 0;
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/* Setup inbound memory window */
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out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
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out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
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out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
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win_idx--;
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paddr += 1ull << mem_log;
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sz -= 1ull << mem_log;
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if (sz) {
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mem_log = __ilog2_u64(sz);
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piwar |= (mem_log - 1);
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out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
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out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
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out_be32(&pci->piw[win_idx].piwar, piwar);
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win_idx--;
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paddr += 1ull << mem_log;
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}
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hose->dma_window_base_cur = 0x00000000;
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hose->dma_window_size = (resource_size_t)paddr;
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}
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if (hose->dma_window_size < mem) {
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#ifndef CONFIG_SWIOTLB
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pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
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"map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
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name);
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#endif
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/* adjusting outbound windows could reclaim space in mem map */
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if (paddr_hi < 0xffffffffull)
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pr_warning("%s: WARNING: Outbound window cfg leaves "
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"gaps in memory map. Adjusting the memory map "
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"could reduce unnecessary bounce buffering.\n",
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name);
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pr_info("%s: DMA window size is 0x%llx\n", name,
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(u64)hose->dma_window_size);
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}
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iounmap(pci);
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}
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@ -180,16 +282,6 @@ static void __init setup_pci_cmd(struct pci_controller *hose)
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}
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}
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static void __init setup_pci_pcsrbar(struct pci_controller *hose)
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{
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#ifdef CONFIG_PCI_MSI
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phys_addr_t immr_base;
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immr_base = get_immrbase();
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early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base);
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#endif
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}
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void fsl_pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
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@ -273,8 +365,6 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
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/* Setup PEX window registers */
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setup_pci_atmu(hose, &rsrc);
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/* Setup PEXCSRBAR */
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setup_pci_pcsrbar(hose);
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return 0;
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}
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@ -16,7 +16,11 @@
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#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
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#define PIWAR_EN 0x80000000 /* Enable */
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#define PIWAR_PF 0x20000000 /* prefetch */
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#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
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#define PIWAR_READ_SNOOP 0x00050000
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#define PIWAR_WRITE_SNOOP 0x00005000
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/* PCI/PCI Express outbound window reg */
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struct pci_outbound_window_regs {
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