forked from luck/tmp_suning_uos_patched
mfd: db8500: Update BML clock register for db8580
BML clock register address in DB8580 has changed.Defined a new address under different name for DB8580. Signed-off-by: Philippe Begnic <philippe.begnic@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -480,6 +480,7 @@ struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
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CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
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CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
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CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
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CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true),
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CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
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CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
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CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
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@ -32,6 +32,7 @@
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#define PRCM_PER7CLK_MGT (0x040)
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#define PRCM_LCDCLK_MGT (0x044)
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#define PRCM_BMLCLK_MGT (0x04C)
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#define PRCM_BML8580CLK_MGT (0x108)
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#define PRCM_HSITXCLK_MGT (0x050)
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#define PRCM_HSIRXCLK_MGT (0x054)
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#define PRCM_HDMICLK_MGT (0x058)
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@ -138,6 +138,7 @@ enum prcmu_clock {
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PRCMU_G1CLK, /* Ux540 only */
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PRCMU_SDMMCHCLK,
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PRCMU_CAMCLK,
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PRCMU_BML8580CLK,
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PRCMU_NUM_REG_CLOCKS,
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PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
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PRCMU_CDCLK,
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