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clk/samsung updates for 5.10

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Minor refactoring removing most of the __clk_lookup() calls.
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Merge tag 'clk-v5.10-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung

Pull Samsung clk driver updates from Sylwester Nawrocki:

Minor refactoring removing most of the __clk_lookup() calls.

* tag 'clk-v5.10-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: Use cached clk_hws instead of __clk_lookup() calls
  clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions
  clk: samsung: Add clk ID definitions for the CPU parent clocks
  clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks
  clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d
  clk: samsung: Keep top BPLL mux on Exynos542x enabled
This commit is contained in:
Stephen Boyd 2020-09-22 12:23:34 -07:00
commit 553be99d1f
9 changed files with 68 additions and 46 deletions
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37
drivers/clk/samsung/clk-cpu.c
View File

@ -401,26 +401,34 @@ static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
/* helper function to register a CPU clock */
int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
unsigned int lookup_id, const char *name, const char *parent,
const char *alt_parent, unsigned long offset,
const struct exynos_cpuclk_cfg_data *cfg,
unsigned int lookup_id, const char *name,
const struct clk_hw *parent, const struct clk_hw *alt_parent,
unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
unsigned long num_cfgs, unsigned long flags)
{
struct exynos_cpuclk *cpuclk;
struct clk_init_data init;
struct clk *parent_clk;
const char *parent_name;
int ret = 0;
if (IS_ERR(parent) || IS_ERR(alt_parent)) {
pr_err("%s: invalid parent clock(s)\n", __func__);
return -EINVAL;
}
cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
if (!cpuclk)
return -ENOMEM;
parent_name = clk_hw_get_name(parent);
init.name = name;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent;
init.parent_names = &parent_name;
init.num_parents = 1;
init.ops = &exynos_cpuclk_clk_ops;
cpuclk->alt_parent = alt_parent;
cpuclk->hw.init = &init;
cpuclk->ctrl_base = ctx->reg_base + offset;
cpuclk->lock = &ctx->lock;
@ -430,23 +438,8 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
else
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
cpuclk->alt_parent = __clk_get_hw(__clk_lookup(alt_parent));
if (!cpuclk->alt_parent) {
pr_err("%s: could not lookup alternate parent %s\n",
__func__, alt_parent);
ret = -EINVAL;
goto free_cpuclk;
}
parent_clk = __clk_lookup(parent);
if (!parent_clk) {
pr_err("%s: could not lookup parent clock %s\n",
__func__, parent);
ret = -EINVAL;
goto free_cpuclk;
}
ret = clk_notifier_register(parent_clk, &cpuclk->clk_nb);
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
if (ret) {
pr_err("%s: failed to register clock notifier for %s\n",
__func__, name);
@ -471,7 +464,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
free_cpuclk_data:
kfree(cpuclk->cfg);
unregister_clk_nb:
clk_notifier_unregister(parent_clk, &cpuclk->clk_nb);
clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);
free_cpuclk:
kfree(cpuclk);
return ret;

6
drivers/clk/samsung/clk-cpu.h
View File

@ -46,7 +46,7 @@ struct exynos_cpuclk_cfg_data {
*/
struct exynos_cpuclk {
struct clk_hw hw;
struct clk_hw *alt_parent;
const struct clk_hw *alt_parent;
void __iomem *ctrl_base;
spinlock_t *lock;
const struct exynos_cpuclk_cfg_data *cfg;
@ -62,9 +62,9 @@ struct exynos_cpuclk {
#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
};
extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
unsigned int lookup_id, const char *name,
const char *parent, const char *alt_parent,
const struct clk_hw *parent, const struct clk_hw *alt_parent,
unsigned long offset,
const struct exynos_cpuclk_cfg_data *cfg,
unsigned long num_cfgs, unsigned long flags);

6
drivers/clk/samsung/clk-exynos3250.c
View File

@ -808,14 +808,16 @@ static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
static void __init exynos3250_cmu_init(struct device_node *np)
{
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
ctx = samsung_cmu_register_one(np, &cmu_info);
if (!ctx)
return;
hws = ctx->clk_data.hws;
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_core_p[0], mout_core_p[1], 0x14200,
e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],
0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
CLK_CPU_HAS_DIV1);
exynos3_core_down_clock(ctx->reg_base);

7
drivers/clk/samsung/clk-exynos4.c
View File

@ -1233,6 +1233,8 @@ static void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc soc)
{
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
exynos4_soc = soc;
reg_base = of_iomap(np, 0);
@ -1240,6 +1242,7 @@ static void __init exynos4_clk_init(struct device_node *np,
panic("%s: failed to map registers\n", __func__);
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
@ -1302,7 +1305,7 @@ static void __init exynos4_clk_init(struct device_node *np,
exynos4210_fixed_factor_clks,
ARRAY_SIZE(exynos4210_fixed_factor_clks));
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_core_p4210[0], mout_core_p4210[1], 0x14200,
hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,
e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
} else {
@ -1317,7 +1320,7 @@ static void __init exynos4_clk_init(struct device_node *np,
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,
e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
}

8
drivers/clk/samsung/clk-exynos5250.c
View File

@ -253,14 +253,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
/*
* CMU_CPU
*/
MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
/*
* CMU_CORE
*/
MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
/*
* CMU_TOP
@ -782,6 +782,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
{
struct samsung_clk_provider *ctx;
unsigned int tmp;
struct clk_hw **hws;
if (np) {
reg_base = of_iomap(np, 0);
@ -792,6 +793,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
}
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
@ -821,7 +823,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks));
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_cpu_p[0], mout_cpu_p[1], 0x200,
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,
exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
CLK_CPU_HAS_DIV1);

30
drivers/clk/samsung/clk-exynos5420.c
View File

@ -596,13 +596,14 @@ static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
SRC_TOP7, 4, 1),
MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p,
SRC_TOP7, 8, 2),
MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p,
SRC_TOP7, 12, 2),
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
@ -712,8 +713,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
SRC_TOP12, 8, 1),
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
SRC_TOP12, 12, 1),
MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
SRC_TOP12, 20, 1),
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
@ -1560,6 +1561,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
enum exynos5x_soc soc)
{
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
if (np) {
reg_base = of_iomap(np, 0);
@ -1572,6 +1574,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_soc = soc;
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
@ -1623,15 +1626,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
if (soc == EXYNOS5420) {
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_cpu_p[0], mout_cpu_p[1], 0x200,
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
} else {
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_cpu_p[0], mout_cpu_p[1], 0x200,
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
}
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
hws[CLK_MOUT_KPLL], hws[CLK_MOUT_MSPLL_KFC], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
samsung_clk_extended_sleep_init(reg_base,
@ -1654,7 +1657,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
* that the internal busses get their clock regardless of the
* main G3D clock enablement status.
*/
clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
/*
* Keep top BPLL mux enabled permanently to ensure that DRAM operates
* properly.
*/
clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
samsung_clk_of_add_provider(np, ctx);
}

10
drivers/clk/samsung/clk-exynos5433.c
View File

@ -3679,6 +3679,7 @@ static void __init exynos5433_cmu_apollo_init(struct device_node *np)
{
void __iomem *reg_base;
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@ -3701,8 +3702,10 @@ static void __init exynos5433_cmu_apollo_init(struct device_node *np)
samsung_clk_register_gate(ctx, apollo_gate_clks,
ARRAY_SIZE(apollo_gate_clks));
hws = ctx->clk_data.hws;
exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
mout_apollo_p[0], mout_apollo_p[1], 0x200,
hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200,
exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
CLK_CPU_HAS_E5433_REGS_LAYOUT);
@ -3933,6 +3936,7 @@ static void __init exynos5433_cmu_atlas_init(struct device_node *np)
{
void __iomem *reg_base;
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@ -3955,8 +3959,10 @@ static void __init exynos5433_cmu_atlas_init(struct device_node *np)
samsung_clk_register_gate(ctx, atlas_gate_clks,
ARRAY_SIZE(atlas_gate_clks));
hws = ctx->clk_data.hws;
exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
mout_atlas_p[0], mout_atlas_p[1], 0x200,
hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200,
exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
CLK_CPU_HAS_E5433_REGS_LAYOUT);

4
include/dt-bindings/clock/exynos5250.h
View File

@ -172,8 +172,10 @@
#define CLK_MOUT_GPLL 1025
#define CLK_MOUT_ACLK200_DISP1_SUB 1026
#define CLK_MOUT_ACLK300_DISP1_SUB 1027
#define CLK_MOUT_APLL 1028
#define CLK_MOUT_MPLL 1029
/* must be greater than maximal clock id */
#define CLK_NR_CLKS 1028
#define CLK_NR_CLKS 1030
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */

6
include/dt-bindings/clock/exynos5420.h
View File

@ -230,6 +230,12 @@
#define CLK_MOUT_USER_MAU_EPLL 659
#define CLK_MOUT_SCLK_SPLL 660
#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
#define CLK_MOUT_SW_ACLK_G3D 662
#define CLK_MOUT_APLL 663
#define CLK_MOUT_MSPLL_CPU 664
#define CLK_MOUT_KPLL 665
#define CLK_MOUT_MSPLL_KFC 666
/* divider clocks */
#define CLK_DOUT_PIXEL 768