forked from luck/tmp_suning_uos_patched
scsi: ufs: ufs-exynos: Add UFS host support for Exynos SoCs
This patch introduces Exynos UFS host controller driver which mainly handles vendor-specific operations including link startup, power mode change and hibernation/unhibernation. [robot: drivers/scsi/ufs/ufs-exynos.c:931:8-10: WARNING: possible condition with no effect (if == else) ] Link: https://lore.kernel.org/r/20200528011658.71590-10-alim.akhtar@samsung.com Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Julia Lawall <julia.lawall@lip6.fr> Tested-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Reviewed-by: Kiwoong Kim <kwmad.kim@samsung.com> Reviewed-by: Avri Altman <avri.altman@wdc.com> Signed-off-by: Seungwon Jeon <essuuj@gmail.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Alim Akhtar
Martin K. Petersen
parent
d779a6e90e
commit
55f4b1f736
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@ -160,3 +160,15 @@ config SCSI_UFS_BSG
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Select this if you need a bsg device node for your UFS controller.
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If unsure, say N.
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config SCSI_UFS_EXYNOS
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bool "EXYNOS specific hooks to UFS controller platform driver"
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depends on SCSI_UFSHCD_PLATFORM && (ARCH_EXYNOS || COMPILE_TEST)
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select PHY_SAMSUNG_UFS
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help
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This selects the EXYNOS specific additions to UFSHCD platform driver.
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UFS host on EXYNOS includes HCI and UNIPRO layer, and associates with
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UFS-PHY driver.
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Select this if you have UFS host controller on EXYNOS chipset.
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If unsure, say N.
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@ -4,6 +4,7 @@ obj-$(CONFIG_SCSI_UFS_DWC_TC_PCI) += tc-dwc-g210-pci.o ufshcd-dwc.o tc-dwc-g210.
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obj-$(CONFIG_SCSI_UFS_DWC_TC_PLATFORM) += tc-dwc-g210-pltfrm.o ufshcd-dwc.o tc-dwc-g210.o
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obj-$(CONFIG_SCSI_UFS_CDNS_PLATFORM) += cdns-pltfrm.o
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obj-$(CONFIG_SCSI_UFS_QCOM) += ufs-qcom.o
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obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos.o
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obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o
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ufshcd-core-y += ufshcd.o ufs-sysfs.o
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ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o
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1292
drivers/scsi/ufs/ufs-exynos.c
Normal file
1292
drivers/scsi/ufs/ufs-exynos.c
Normal file
File diff suppressed because it is too large
Load Diff
287
drivers/scsi/ufs/ufs-exynos.h
Normal file
287
drivers/scsi/ufs/ufs-exynos.h
Normal file
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@ -0,0 +1,287 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* UFS Host Controller driver for Exynos specific extensions
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*
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* Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
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*
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*/
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#ifndef _UFS_EXYNOS_H_
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#define _UFS_EXYNOS_H_
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/*
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* UNIPRO registers
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*/
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#define UNIPRO_DBG_FORCE_DME_CTRL_STATE 0x150
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/*
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* MIBs for PA debug registers
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*/
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#define PA_DBG_CLK_PERIOD 0x9514
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#define PA_DBG_TXPHY_CFGUPDT 0x9518
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#define PA_DBG_RXPHY_CFGUPDT 0x9519
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#define PA_DBG_MODE 0x9529
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#define PA_DBG_SKIP_RESET_PHY 0x9539
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#define PA_DBG_OV_TM 0x9540
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#define PA_DBG_SKIP_LINE_RESET 0x9541
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#define PA_DBG_LINE_RESET_REQ 0x9543
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#define PA_DBG_OPTION_SUITE 0x9564
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#define PA_DBG_OPTION_SUITE_DYN 0x9565
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/*
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* MIBs for Transport Layer debug registers
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*/
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#define T_DBG_SKIP_INIT_HIBERN8_EXIT 0xc001
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/*
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* Exynos MPHY attributes
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*/
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#define TX_LINERESET_N_VAL 0x0277
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#define TX_LINERESET_N(v) (((v) >> 10) & 0xFF)
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#define TX_LINERESET_P_VAL 0x027D
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#define TX_LINERESET_P(v) (((v) >> 12) & 0xFF)
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#define TX_OV_SLEEP_CNT_TIMER 0x028E
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#define TX_OV_H8_ENTER_EN (1 << 7)
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#define TX_OV_SLEEP_CNT(v) (((v) >> 5) & 0x7F)
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#define TX_HIGH_Z_CNT_11_08 0x028C
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#define TX_HIGH_Z_CNT_H(v) (((v) >> 8) & 0xF)
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#define TX_HIGH_Z_CNT_07_00 0x028D
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#define TX_HIGH_Z_CNT_L(v) ((v) & 0xFF)
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#define TX_BASE_NVAL_07_00 0x0293
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#define TX_BASE_NVAL_L(v) ((v) & 0xFF)
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#define TX_BASE_NVAL_15_08 0x0294
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#define TX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF)
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#define TX_GRAN_NVAL_07_00 0x0295
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#define TX_GRAN_NVAL_L(v) ((v) & 0xFF)
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#define TX_GRAN_NVAL_10_08 0x0296
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#define TX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3)
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#define RX_FILLER_ENABLE 0x0316
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#define RX_FILLER_EN (1 << 1)
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#define RX_LINERESET_VAL 0x0317
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#define RX_LINERESET(v) (((v) >> 12) & 0xFF)
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#define RX_LCC_IGNORE 0x0318
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#define RX_SYNC_MASK_LENGTH 0x0321
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#define RX_HIBERN8_WAIT_VAL_BIT_20_16 0x0331
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#define RX_HIBERN8_WAIT_VAL_BIT_15_08 0x0332
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#define RX_HIBERN8_WAIT_VAL_BIT_07_00 0x0333
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#define RX_OV_SLEEP_CNT_TIMER 0x0340
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#define RX_OV_SLEEP_CNT(v) (((v) >> 6) & 0x1F)
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#define RX_OV_STALL_CNT_TIMER 0x0341
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#define RX_OV_STALL_CNT(v) (((v) >> 4) & 0xFF)
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#define RX_BASE_NVAL_07_00 0x0355
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#define RX_BASE_NVAL_L(v) ((v) & 0xFF)
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#define RX_BASE_NVAL_15_08 0x0354
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#define RX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF)
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#define RX_GRAN_NVAL_07_00 0x0353
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#define RX_GRAN_NVAL_L(v) ((v) & 0xFF)
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#define RX_GRAN_NVAL_10_08 0x0352
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#define RX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3)
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#define CMN_PWM_CLK_CTRL 0x0402
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#define PWM_CLK_CTRL_MASK 0x3
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#define IATOVAL_NSEC 20000 /* unit: ns */
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#define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate)
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struct exynos_ufs;
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/* vendor specific pre-defined parameters */
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#define SLOW 1
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#define FAST 2
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#define UFS_EXYNOS_LIMIT_NUM_LANES_RX 2
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#define UFS_EXYNOS_LIMIT_NUM_LANES_TX 2
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#define UFS_EXYNOS_LIMIT_HSGEAR_RX UFS_HS_G3
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#define UFS_EXYNOS_LIMIT_HSGEAR_TX UFS_HS_G3
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#define UFS_EXYNOS_LIMIT_PWMGEAR_RX UFS_PWM_G4
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#define UFS_EXYNOS_LIMIT_PWMGEAR_TX UFS_PWM_G4
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#define UFS_EXYNOS_LIMIT_RX_PWR_PWM SLOW_MODE
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#define UFS_EXYNOS_LIMIT_TX_PWR_PWM SLOW_MODE
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#define UFS_EXYNOS_LIMIT_RX_PWR_HS FAST_MODE
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#define UFS_EXYNOS_LIMIT_TX_PWR_HS FAST_MODE
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#define UFS_EXYNOS_LIMIT_HS_RATE PA_HS_MODE_B
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#define UFS_EXYNOS_LIMIT_DESIRED_MODE FAST
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#define RX_ADV_FINE_GRAN_SUP_EN 0x1
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#define RX_ADV_FINE_GRAN_STEP_VAL 0x3
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#define RX_ADV_MIN_ACTV_TIME_CAP 0x9
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#define PA_GRANULARITY_VAL 0x6
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#define PA_TACTIVATE_VAL 0x3
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#define PA_HIBERN8TIME_VAL 0x20
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#define PCLK_AVAIL_MIN 70000000
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#define PCLK_AVAIL_MAX 133000000
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struct exynos_ufs_uic_attr {
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/* TX Attributes */
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unsigned int tx_trailingclks;
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unsigned int tx_dif_p_nsec;
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unsigned int tx_dif_n_nsec;
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unsigned int tx_high_z_cnt_nsec;
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unsigned int tx_base_unit_nsec;
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unsigned int tx_gran_unit_nsec;
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unsigned int tx_sleep_cnt;
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unsigned int tx_min_activatetime;
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/* RX Attributes */
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unsigned int rx_filler_enable;
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unsigned int rx_dif_p_nsec;
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unsigned int rx_hibern8_wait_nsec;
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unsigned int rx_base_unit_nsec;
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unsigned int rx_gran_unit_nsec;
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unsigned int rx_sleep_cnt;
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unsigned int rx_stall_cnt;
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unsigned int rx_hs_g1_sync_len_cap;
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unsigned int rx_hs_g2_sync_len_cap;
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unsigned int rx_hs_g3_sync_len_cap;
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unsigned int rx_hs_g1_prep_sync_len_cap;
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unsigned int rx_hs_g2_prep_sync_len_cap;
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unsigned int rx_hs_g3_prep_sync_len_cap;
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/* Common Attributes */
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unsigned int cmn_pwm_clk_ctrl;
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/* Internal Attributes */
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unsigned int pa_dbg_option_suite;
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/* Changeable Attributes */
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unsigned int rx_adv_fine_gran_sup_en;
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unsigned int rx_adv_fine_gran_step;
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unsigned int rx_min_actv_time_cap;
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unsigned int rx_hibern8_time_cap;
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unsigned int rx_adv_min_actv_time_cap;
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unsigned int rx_adv_hibern8_time_cap;
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unsigned int pa_granularity;
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unsigned int pa_tactivate;
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unsigned int pa_hibern8time;
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};
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struct exynos_ufs_drv_data {
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char *compatible;
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struct exynos_ufs_uic_attr *uic_attr;
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unsigned int quirks;
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unsigned int opts;
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/* SoC's specific operations */
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int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
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int (*pre_link)(struct exynos_ufs *ufs);
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int (*post_link)(struct exynos_ufs *ufs);
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int (*pre_pwr_change)(struct exynos_ufs *ufs,
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struct ufs_pa_layer_attr *pwr);
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int (*post_pwr_change)(struct exynos_ufs *ufs,
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struct ufs_pa_layer_attr *pwr);
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};
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struct ufs_phy_time_cfg {
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u32 tx_linereset_p;
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u32 tx_linereset_n;
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u32 tx_high_z_cnt;
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u32 tx_base_n_val;
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u32 tx_gran_n_val;
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u32 tx_sleep_cnt;
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u32 rx_linereset;
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u32 rx_hibern8_wait;
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u32 rx_base_n_val;
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u32 rx_gran_n_val;
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u32 rx_sleep_cnt;
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u32 rx_stall_cnt;
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};
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struct exynos_ufs {
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struct ufs_hba *hba;
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struct phy *phy;
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void __iomem *reg_hci;
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void __iomem *reg_unipro;
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void __iomem *reg_ufsp;
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struct clk *clk_hci_core;
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struct clk *clk_unipro_main;
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struct clk *clk_apb;
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u32 pclk_rate;
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u32 pclk_div;
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u32 pclk_avail_min;
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u32 pclk_avail_max;
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u32 mclk_rate;
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int avail_ln_rx;
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int avail_ln_tx;
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int rx_sel_idx;
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struct ufs_pa_layer_attr dev_req_params;
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struct ufs_phy_time_cfg t_cfg;
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ktime_t entry_hibern8_t;
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struct exynos_ufs_drv_data *drv_data;
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u32 opts;
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#define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL BIT(0)
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#define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB BIT(1)
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#define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL BIT(2)
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#define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3)
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#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
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};
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#define for_each_ufs_rx_lane(ufs, i) \
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for (i = (ufs)->rx_sel_idx; \
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i < (ufs)->rx_sel_idx + (ufs)->avail_ln_rx; i++)
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#define for_each_ufs_tx_lane(ufs, i) \
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for (i = 0; i < (ufs)->avail_ln_tx; i++)
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#define EXYNOS_UFS_MMIO_FUNC(name) \
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static inline void name##_writel(struct exynos_ufs *ufs, u32 val, u32 reg)\
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{ \
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writel(val, ufs->reg_##name + reg); \
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} \
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\
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static inline u32 name##_readl(struct exynos_ufs *ufs, u32 reg) \
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{ \
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return readl(ufs->reg_##name + reg); \
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}
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EXYNOS_UFS_MMIO_FUNC(hci);
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EXYNOS_UFS_MMIO_FUNC(unipro);
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EXYNOS_UFS_MMIO_FUNC(ufsp);
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#undef EXYNOS_UFS_MMIO_FUNC
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long exynos_ufs_calc_time_cntr(struct exynos_ufs *, long);
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static inline void exynos_ufs_enable_ov_tm(struct ufs_hba *hba)
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{
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), TRUE);
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}
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static inline void exynos_ufs_disable_ov_tm(struct ufs_hba *hba)
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{
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), FALSE);
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}
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static inline void exynos_ufs_enable_dbg_mode(struct ufs_hba *hba)
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{
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), TRUE);
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}
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static inline void exynos_ufs_disable_dbg_mode(struct ufs_hba *hba)
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{
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), FALSE);
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}
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struct exynos_ufs_drv_data exynos_ufs_drvs;
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struct exynos_ufs_uic_attr exynos7_uic_attr = {
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.tx_trailingclks = 0x10,
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.tx_dif_p_nsec = 3000000, /* unit: ns */
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.tx_dif_n_nsec = 1000000, /* unit: ns */
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.tx_high_z_cnt_nsec = 20000, /* unit: ns */
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.tx_base_unit_nsec = 100000, /* unit: ns */
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.tx_gran_unit_nsec = 4000, /* unit: ns */
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.tx_sleep_cnt = 1000, /* unit: ns */
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.tx_min_activatetime = 0xa,
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.rx_filler_enable = 0x2,
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.rx_dif_p_nsec = 1000000, /* unit: ns */
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.rx_hibern8_wait_nsec = 4000000, /* unit: ns */
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.rx_base_unit_nsec = 100000, /* unit: ns */
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.rx_gran_unit_nsec = 4000, /* unit: ns */
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.rx_sleep_cnt = 1280, /* unit: ns */
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.rx_stall_cnt = 320, /* unit: ns */
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.rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
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.rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
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.rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
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.rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
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.rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
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.rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
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.pa_dbg_option_suite = 0x30103,
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};
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#endif /* _UFS_EXYNOS_H_ */
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@ -64,8 +64,25 @@
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#define CFGRXOVR4 0x00E9
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#define RXSQCTRL 0x00B5
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#define CFGRXOVR6 0x00BF
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#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B
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#define RX_HS_G1_PREP_LENGTH_CAP 0x008C
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#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094
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#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095
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#define RX_HS_G2_PREP_LENGTH_CAP 0x0096
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#define RX_HS_G3_PREP_LENGTH_CAP 0x0097
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#define RX_ADV_GRANULARITY_CAP 0x0098
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#define RX_MIN_ACTIVATETIME_CAP 0x008F
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#define RX_HIBERN8TIME_CAP 0x0092
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#define RX_ADV_HIBERN8TIME_CAP 0x0099
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#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A
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#define is_mphy_tx_attr(attr) (attr < RX_MODE)
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#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
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#define SYNC_LEN_FINE(x) ((x) & 0x3F)
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#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F))
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#define PREP_LEN(x) ((x) & 0xF)
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#define RX_MIN_ACTIVATETIME_UNIT_US 100
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#define HIBERN8TIME_UNIT_US 100
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@ -124,6 +141,7 @@
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#define PA_PACPREQEOBTIMEOUT 0x1591
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#define PA_HIBERN8TIME 0x15A7
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#define PA_LOCALVERINFO 0x15A9
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#define PA_GRANULARITY 0x15AA
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#define PA_TACTIVATE 0x15A8
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#define PA_PACPFRAMECOUNT 0x15C0
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#define PA_PACPERRORCOUNT 0x15C1
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@ -291,4 +309,19 @@ enum {
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TRUE,
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};
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/* CPort setting */
|
||||
#define E2EFC_ON (1 << 0)
|
||||
#define E2EFC_OFF (0 << 0)
|
||||
#define CSD_N_ON (0 << 1)
|
||||
#define CSD_N_OFF (1 << 1)
|
||||
#define CSV_N_ON (0 << 2)
|
||||
#define CSV_N_OFF (1 << 2)
|
||||
#define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF)
|
||||
|
||||
/* CPort connection state */
|
||||
enum {
|
||||
CPORT_IDLE = 0,
|
||||
CPORT_CONNECTED,
|
||||
};
|
||||
|
||||
#endif /* _UNIPRO_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user